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參數(shù)資料
| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 18/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
write-per-bit
The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit
operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling edge of
RAS, the write operation is performed without any masking. The SMJ55161 offers two write-per-bit modes:
nonpersistent write-per-bit and persistent write-per-bit.
nonpersistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit
mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask
selects which of the 16 I/Os are to be written and which are not. After RAS has latched the on-chip write-per-bit
mask, input data is driven onto the DQ pins and is latched on either the first falling edge of CASx or the falling
edge of WE, whichever occurs later. CASL enables the lower byte (DQ0–DQ7) to be written through the mask
and CASU enables the upper byte (DQ8–DQ15) to be written through the mask. If a data low (write mask = 0)
is strobed into a particular I/O pin on the falling edge of RAS, data is not written to that I/O. If a data high
(write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS, data is written to that I/O
(see Figure 7).
RAS
CASL
CASU
WE
DQ0–DQ15
Valid Input
th(WLD)
tsu(DQR)
tsu(DWL)
th(RDQ)
Write Mask
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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