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| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 29/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
split-register programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CASx
and WE low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4–A7 which are used to define the SAM’s partition length. The other row-address inputs are don’t cares.
Stop-point mode should be initiated after the initialization cycles are performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
MAXIMUM
PARTITION
LENGTH
ADDRESS AT RAS IN CBRS CYCLE
NUMBER OF
PARTITIONS
STOP POINT LOCATIONS
STOP-POINT LOCATIONS
A8
A7
A6
A5
A4
A0–A3
16
X
L
L
L
L
X
16
15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,
191, 207, 223, 239, 255
32
X
L
L
L
H
X
8
31, 63, 95, 127, 159, 191, 223, 255
64
X
L
L
H
H
X
4
63, 127, 191, 255
128
(default)
X
L
H
H
H
X
2
127, 255
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines the SAM
partition in which the serial output begins and at which stop point the serial output stops coming from one half
of the SAM and switches to the opposite half of the SAM (see Figure 25).
255
128
0
127
RAS
Read XFER
Split
Read XFER
Split
Tap = H1
SC
191
Tap = L1
Tap = H2
L1
63
H2
Read XFER
Split
Tap = L2
255
L2
63
191
SAM High Half
SAM Low Half
H1
L1
H1
Read XFER
Full
L2
H2
Figure 25. Example of Split-Register Operation With Programmable Stop Points
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