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參數(shù)資料
| 型號(hào)： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
persistent write-per-bit
The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is overwritten but remains valid over an arbitrary number
of write cycles until another LMR cycle is performed or power is removed.
The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS and
held low on the first falling edge of CASx. A binary code is input to the write-mask register via the random I/O
pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. Byte
write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then
be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling
edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and
is reset only by a CBR refresh (option-reset) cycle (see Figure 8).
RAS
CASx
A0–A8
DSF
Load-Write-Mask Register
Persistent Write-Per-Bit
DQ0–
DQ15
Write-Mask
Data
Valid
Input
CBR Refresh (option reset)
WE
Refresh
Address
Row
Column
Mask Data = 1: Write to I/O enabled
= 0: Write to I/O disabled
Figure 8. Example of a Persistent Write-Per-Bit Operation
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