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| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 45/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CASx
A0–A8
WE
TRG
DSF
DQ0–DQ15
tw(RL)P
td(RLCH)
tc(RDWP)
td(RLCL)
tw(CL)
tw(CH)
td(CLRH)
tw(RH
td(CHRL)
tsu(RA)
tsu(CA)
th(RA)
th(RLCA)
1
2
2
3
4
tsu(SFR)
th(SFR)
tsu(SFC)
th(SFC)
tsu(rd)
tsu(WMR)
td(CLWL)
td(CAWL)
td(RLWL)
tsu(WCH)
td(GHD)
ta(R) (see Note A)
tdis(G)
Row
Column
Column
Valid Out
5
Valid Out
ta(C) (see Note A)
td(DCL)
td(DGL)
td(RLCA)
td(CHRL)
th(RDQ)
tsu(DQR)
tsu(TRG)
th(TRG)
td(DCL)
ta(CA) (see Note A)
th(WLD)
tw(TRG)
tsu(WRH)
th(SFC)
tw(WL)
td(CLGH)
tsu(DWL)
td(DGL)
th(RWM)
td(CLGH)
tw(TRG)
5
tsu(DWL)
th(WLD)
td(GHD)
th(CLCA)
tsu(SFC)
tsu(WCH)
ta(CP) (see Note A)
ta(C) (see Note A)
ta(G) (see Note A)
td(CACH)
td(CARH)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
Figure 36. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 11. Enhanced-Page-Mode Read-Modify-Write-Cycle State Table
CYCLE
STATE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
L
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
L
L
Don’t care
Valid data
Load write-mask register on either the first falling edge of
CASx or the falling edge of WE, whichever occurs later.
Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care
during this cycle.
H
L
H
Don’t care
Write mask
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