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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
7
1999-02-10
I
2
C-Bus interface
P-MQFP-64-3
5 V supply voltage for input signals
3.3 V or 5 V supply voltage for output signals
1.2
The SDA 9206 is a single monolithic IC containing three separate 8-Bit A/D converters
for video (YUV) applications and a clock sync generator which is delivering the sample
clock for the A/D converters. It utilizes an advanced VLSI 0.5
μ
m CMOS process
providing 30 MHz sampling rates at 8-Bits.
General Description
The YUV processing consists of following functional blocks:
Analog input buffers and clamping circuits
Three 30 MHz A/D converters
Digital decimation filters
Delay compensation in Y-path
Output formatter and buffer
The clock sync generator consists essentially of the following functional blocks:
Analog clamping
7-Bit A/D converter
Sync processor with digital horizontal PLL, vertical sync processor
and pulse generator
Clock generator with discrete timing oscillator, D/A converter,
analog PLL and divider, as well as a crystal oscillator
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