參數(shù)資料
型號(hào)： sda 9206
廠(chǎng)商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 25/54頁(yè)
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
25
1999-02-10
2.3.3
The clock sync generator supplies the following pulses:
HS
VS
BLN
Two clamping pulses H1 and H2. H2 is also the internal clamping pulse of
the YUV-ADCs.
The HS pulse is 16 13.5 MHz clock periods long and can be shifted by the
I
2
C-Bus in
increments of four 13.5 MHz clock periods.
For the VS pulse refer to vertical noise suppression.
With the BLN pulse the start time (high-to-low edge) and the stop time (low-to-high
edge) can be set within a certain range of lines in increments of 13.5 MHz clock
periods by
I
2
C Bus. The timing of BLN does not change during
the field blanking interval.
During the BLN pulse the Y-U-V output data are set to their clamping level.
For pulse H1 the start time (low-to-high edge) and stop time can be set in increments
of two 13.5 MHz clock periods.
For pulse H2 the start time (low-to-high edge) and stop time can be set in increments
of 13.5 MHz clock periods.
The timing of the BLN, H1, H2, VS and HS pulses can be set by the costumer using the
specified
I
2
C-Bus bits.
Figure 9
shows the ranges of those settings.
Pulse Generation
Figure 16
I
2
C-Bus Programming Areas of Horizontal-Frequency Pulses
BURST
Reference Time
approx. 2.6 s
(-35.22 s ... 28.42 s)
approx. 1.2 s
H1OF (-28.27 s ... 9.47 s)
H1ON (-28.27 s ... 9.47 s)
H2ON (-4.67 s ... 14.21 s)
H2OF (-4.67 s ... 14.21 s)
BON (-8.89 s ... 9.99 s)
BOF (0.59 s ... 19.46 s)
UET10465
SYNC
HS
H1
H2
BLN
HSON
All times are given in relation to the Reference Time!
All times are only valid for 2FH = 0. If 2FH = 1 all times have to be divided by two!
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