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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
33
1999-02-10
Subaddress 06
H
Bit
D7
Name
TV
Function
Selection of HPLL lock-in behavior:
0:
Optimum for VCR
1:
Optimum for SYNC from network
Generation of V pulse:
0:
V derived from SYNC
1:
Free-running generation; vertical frequency is
determined by VF bit, VOFF bit is enabled, SCHW bit
should be set to 1
Vertical noise suppression:
0:
Noise suppression enabled
1:
No noise suppression
Number of lines per field:
0:
312.5 or 312
1:
262.5 or 262
Note:
VF must be set to the number of lines present in SYNC for
fly-wheel and noise suppression modes. VF determines
the number of lines per field for the free-running or
terminal mode.
Terminal mode:
FREE
TERM SCHW
D6
FREE
D5
VOFF
D4
VF
D3
TERM
VF
Number of Lines
per Field generated
in Free-Running Mode
don’t care
don’t care
1
1
1
1
1
1
0
0
0
0
don’t care
don’t care
1
1
0
0
0
1
0
1
0
1
312
262
312.5
262.5
339
279
D2
GENMOD Clock generator mode
0:
1:
Normal PLL mode
Generator mode (fixed frequency output,
controlled by INC)
D1
D0
0
SYPOL
Reserved
SYNC polarity:
0:
1:
Negative sync signals (normal SYNC input)
Positive sync signals
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