參數(shù)資料
型號: sda 9206
廠商: SIEMENS AG
英文描述: ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述: 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器(帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器)
文件頁數(shù): 19/54頁
文件大?。?/td> 530K
代理商: SDA 9206
SDA 9206
Semiconductor Group
19
1999-02-10
X
AB
:
Z: Pin is in tristate mode.
The BLN signal marks the active part of the video line (
see figure 14
).
X: signal component
A: sample number
B: bit number
Figure 14
Output
Pin
Quasiparallel Data
FORMAT = 10 or 11
(13.5 MHz)
Y
07
Y
17
Y
06
Y
16
Y
05
Y
15
Y
04
Y
14
Y
03
Y
13
Y
02
Y
12
Y
01
Y
11
Y
00
Y
10
U
07
U
05
U
06
U
04
V
07
V
05
V
06
V
04
Z
Z
Z
Z
Z
Z
Z
Z
Parallel Data
FORMAT = 01
(13.5 MHz)
Y
07
Y
06
Y
05
Y
04
Y
03
Y
02
Y
01
Y
00
U
07
U
06
U
05
U
04
U
03
U
02
U
01
U
00
CCIR 656
FORMAT = 00
(27 MHz)
U
07
U
06
U
05
U
04
U
03
U
02
U
01
U
00
Z
Z
Z
Z
Z
Z
Z
Z
PAQ7
PAQ6
PAQ5
PAQ4
PAQ3
PAQ2
PAQ1
PAQ0
PBQ7
PBQ6
PBQ5
PBQ4
PBQ3
PBQ2
PBQ1
PBQ0
Y
27
Y
26
Y
25
Y
24
Y
23
Y
22
Y
21
Y
20
U
03
U
02
V
03
V
02
Z
Z
Z
Z
Y
37
Y
36
Y
35
Y
34
Y
33
Y
32
Y
31
Y
30
U
01
U
00
V
01
V
00
Z
Z
Z
Z
Y
17
Y
16
Y
15
Y
14
Y
13
Y
12
Y
11
Y
10
V
07
V
06
V
05
V
04
V
03
V
02
V
01
V
00
Y
07
Y
06
Y
05
Y
04
Y
03
Y
02
Y
01
Y
00
Z
Z
Z
Z
Z
Z
Z
Z
V
07
V
06
V
05
V
04
V
03
V
02
V
01
V
00
Z
Z
Z
Z
Z
Z
Z
Z
Y
17
Y
16
Y
15
Y
14
Y
13
Y
12
Y
11
Y
10
Z
Z
Z
Z
Z
Z
Z
Z
U0
Y0
V0
Y1
Y0 / U0
Y1 / V0
UED10462
PAQ, PBQ
BLN
PAQ
CLK1
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