參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 34/54頁(yè)
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
34
1999-02-10
Subaddress 07
H
Bit
D7
Name
2FH
Function
Selection of input frequency range:
0:
Normal line frequencies (around 15.6 kHz)
1:
Double line frequencies (31.2...38 kHz)
[YUV A/D converters are switched off]
Maximum width of HSYNC (input SYNC):
0:
6.2
μ
s for low FH-range
3.1
μ
s for high FH-range
(2FH = 1)
1:
9.0
μ
s for low FH-range
4.5
μ
s for high FH-range (2FH = 1)
Minimum width of HSYNC (input SYNC):
0:
3.0
μ
s for low FH-range
1.5
μ
s for high FH-range
(2FH = 1)
1:
1.7
μ
s for low FH-range
0.8
μ
s for high FH-range
(2FH = 1)
Nominal PLL output frequency: INC = 00110
For the allowed values of INC refer to table
chapter 2.3.1
!
Calculation of INC for low FH range:
D6
HSWMA
D5
HSWMI
D4...D0
INC
for high FH range (2FH = 1):
INC
INT
f
f
q
--- * 110592
64 625
,
–
=
INC
INT
f
f
q
--- * 55292
64 625
,
–
=
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