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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
31
1999-02-10
Subaddress 03
H
Bit
D7...D4
D3...D2
Subaddress 04
H
Bit
D7
D6
Name
0000
CGSUP
Function
Reserved
Suppression of black level disturbances caused by copy
guarded tapes
00:
No function
01:
Black level error is limited to + / - 32 (~ 27 mV)
10:
Black level error is limited to + / - 16 (~ 14 mV)
11:
Black level error is limited to + / - 8 (~ 7 mV)
Width of Window in Vertical Processing:
00:
Narrow window: open from line 312 for PAL and 262
for NTSC
01:
Window: open from line 300 for PAL and 250 for NTSC
10:
Window: open from line 290 for PAL and 240 for NTSC
11:
Very wide window: open from line 250 for PAL and
200 for NTSC
D1...D0
VWIWI
Name
0
OEFB
Function
Reserved
Output enable for Featurebox signals BLN, HS and VS:
0:
BLN, HS, VS outputs tristate
1:
BLN, HS, VS outputs enabled (2FH = 0)
BLN, HS outputs enabled, VS output tristate (2FH = 1)
Selection of clock frequency on pin CLK1:
00:
Tristate
01:
6.75 MHz
10:
13.5 MHz
11:
27 MHz
For the allowed values of S1CL refer to table
chapter 2.3.1
!
Selection of clock frequency on pin CLK2:
00:
Tristate
01:
6.75 MHz
10:
13.5 MHz
11:
27 MHz
For the allowed values of S2CL refer to table
chapter 2.3.1
!
Reserved
D5...D4
S1CL
D3...D2
S2CL
D1...D0
00
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