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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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P-MQFP-64-3
Semiconductor Group
6
1999-02-10
ADC with Built in Antialiasing filter and
Clock generation UnitS
ABACUS
SDA 9206
CMOS
Type
SDA 9206
Ordering Code
Q67101-H5185-A704
Package
P-MQFP-64-3
Preliminary Data
1
Overview
1.1
Three equivalent CMOS A/D converters on chip
30 MHz sampling rate
8-Bit resolution
No external sample & hold required
Internal clamping circuits for each of the ADCs
Internal amplification of input signals
can be set by
I
2
C Bus
Internal pre-filtering of analog input signals
High performance decimation filters
Two data sampling modes (4:2:2 and 4:1:1)
3 output data interfaces
- CCIR 656 interface (8 wires)
- Parallel data interface (2 x 8 wires)
- Quasi Parallel data interface (8 + 4 wires)
Overflow and underflow
I
2
C status bits
On-chip sync and clock generation
Separate SYNC input with clamping for sync and clock generation
(max. line frequency of SYNC input: 38 kHz)
positive and negative polarity of SYNC signal (switchable by
I
2
C Bus)
Lock-in behavior can be set via
I
2
C Bus
Frequency generator function possible with digitally adjustable frequency
Clock generation for single and double line input frequencies supported
(1fh / 2fh mode)
Vertical noise suppression and 50/60 Hz detection (for 1fh mode only)
Features
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