參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 27/54頁(yè)
文件大小： 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
27
1999-02-10
2.4
I
2
C Bus
2.4.1
I
2
C-Bus Address
2.4.2
I
2
C-Bus Format
Write:
Read:
Reading starts with status byte 0, followed by status byte 1 and then in succession by
data byte n, data byte n+1..., where n is the last write address. Specification of a
subaddress in reading mode is not possible.
S:
Start condition
A:
Acknowledge
P:
Stop condition
NA:
Not Acknowledge
An automatic address increment function is implemented.
After switching on the IC or RESIN = 0, all bits are set to defined states. Particularly:
1 0 1 1 0 0 B
B: equal to the value set on pin ADR0
S 1 0 1 1 0 0 B 0 A
Subaddress
A
Data Byte
A
*****
A
P
S 1 0 1 1 0 0 B 1 A
· · ·
Status Byte 0
A
Status Byte 1
A Data****
**** Byte n A Data Byte (n+1) A
*****
NA P
Register
00
H
01
H
02
H
03
H
04
H
05
H
06
H
07
H
08
H
09
H
0A
H
0B
H
Default value
10
H
40
H
00
H
00
H
28
H
00
H
00
H
06
H
00
H
00
H
00
H
00
H
Register
0C
H
0D
H
0E
H
0F
H
10
H
11
H
12
H
13
H
14
H
15
H
16
H
17
H
Default value
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
13
H
00
H
00
H
00
H
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