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參數(shù)資料
| 型號(hào)： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 16/54頁 |
| 文件大小： | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
16
1999-02-10
2.1.3
The analog pins AINY, AINU, AINV are switched simultaneously to on chip generated
clamping levels by an on chip clamping pulse H2.
Clamping
The external clamping capacitance is loaded by on chip current sources during
clamping. So loading time depends on the values of
C
ext cl
.
2.1.4
The data rates of digital YUV signals are reduced in decimation filters following the
A/D conversion. The overall performance of the decimation filters is tuned to the
requirements for TV signals.
In
figure 11
the frequency response of the filter for the Y channel is shown. The input
sampling rate is 27 MHz, the output sampling rate is 13.5 MHz.
Digital Decimation Filters for YUV
Figure 11
Magnitude Frequency Response of the Luminance Filter
The Input Sampling Frequency
f
S
is 27 MHz
Analog Channel
Straight Binary
Code
0001 0000
1000 0000
Two’s Complement
Code
1001 0000
0000 0000
Components
AINY
AINU, AINV
Y
U, V
UED10459
0
-50
A
-40
-30
-20
-10
0
10
dB
0.1
0.2
0.3
0.4
0.5
S
f
f /
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