參數(shù)資料
型號(hào): sda 9206
廠商: SIEMENS AG
英文描述: ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述: 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器)
文件頁(yè)數(shù): 32/54頁(yè)
文件大?。?/td> 530K
代理商: SDA 9206
SDA 9206
Semiconductor Group
32
1999-02-10
Subaddress 05
H
Bit
D7
D6
Name
0
SCHW
Function
Reserved
Mode of vertical pulse generation:
0:
No flywheel mode
1:
Flywheel mode
Relationship between horizontal frequency in SYNC and default
frequency on CLK1 and CLK2:
0:
864
1:
858
Minimum sync pulse length from which a vertical pulse is
detected:
0:
26.6
μ
s
1:
11.3
μ
s
Clamping of SYNC for clock generator:
0:
Clamping on
1:
Clamping off
Reserved
D5
HPLL
D4
VTHRE
D3
CLOF
D2...D0
000
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