參數(shù)資料
型號: sda 9206
廠商: SIEMENS AG
英文描述: ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述: 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器(帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器)
文件頁數(shù): 24/54頁
文件大小: 530K
代理商: SDA 9206
SDA 9206
Semiconductor Group
24
1999-02-10
Figure 15
Window for Vertical Pulse Noise Suppression
xxx
249
289
298
299
300
311
312
Line Number
Interference Pulse
Non-Suppressed
Vertical Sync
from HPLL
Window
(VWIWI = 11)
(VWIWI = 10)
Window
(VWIWI = 01)
Window
(VWIWI = 00)
Window
(noise-suppressed)
(199) (200)
(239) (240)
(250)
(249)
(262)
(261)
Vertical Sync
Closes
Window
Suppression of Interference
Pulse not in Window
Numbers in Brackets for 525 Lines per Frame
UED10463
VS
312
313
339
1
Line Number
Windows
Numbers in Brackets for 525 Lines per Frame
UED10464
272
(262)
(279)
(1)
(242)
SCHW = 0
When missing Vertical Sync from HPLL:
RC-Opening
(Independent from WWW Bit)
VS
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