參數(shù)資料
型號: sda 9206
廠商: SIEMENS AG
英文描述: ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內去混疊和時鐘發(fā)生器的A/D轉換器)
中文描述: 在抗混疊濾波器和時鐘產生單元內置模數(shù)轉換器(帶有片內去混疊和時鐘發(fā)生器的的A / D轉換器)
文件頁數(shù): 51/54頁
文件大小: 530K
代理商: SDA 9206
SDA 9206
Semiconductor Group
51
1999-02-10
Figure 20
Application Circuit 3
5
6
1V
ADDY
V
AGNDY
V
ADDU
AGNDU
V
15
AGNDV
ADDC
10V
11
V
V
V
V
V
64
60
59
AGNDC
ADDPA
ADDV
58
AGNDPA
+
C
11
10 F
2
L
10 H
V
DDQ
SSQ
V
V
V
V
V
DD
SS
35
C
100 nF
C
100 nF
C
54
100 nF
C
55
100 nF
C
56
100 nF
12
2.2 H
L
μ
1
+5 V
R
8.2 /
2%
4
+
V
REFHY
V
REFHU
V
REFHC
V
REFHV
2
7
12
63
C
49
48
C
50
C
10
C
100 nF
100 nF
100 nF
100 nF
7
1 F
C
1 F
C
8
C
+
1
2
3
TL 431
D1
2%
62 /
R
3
2
R
2%
R
16 /
1
2%
REFLV
REFLC
REFLU
V
V
V
REFLY
V
51
52
C
53
C
9
C
100 nF
100 nF
100 nF
100 nF
4
9
14
61
32
23
45
36
50
55
46
49
21
22
44
43
42
41
40
39
38
37
31
30
29
28
27
26
25
24
20
57
54
53
17
52
19
51
18
56
47
SSQ
DDQ
DDDTO
SSDTO
V
V
PBQ0
PBQ1
PBQ2
PBQ3
PBQ4
PBQ5
PBQ6
PBQ7
PAQ0
PAQ1
PAQ2
PAQ3
PAQ4
PAQ5
PAQ6
PAQ7
H2I2
EXSYN
V
V
DD
SS
+
13
10 F
C
10 H
L
3
C
14
100 nF
100 nF
15
C
CLK2
BLN
VS
H1I1
CLK1
HS
RESOUTN
TEST
AINY
AINU
AINV
SYNC
100 nF
100 nF
100 nF
100 nF
6
C
5
C
4
C
3
C
ADR0
SCL
SDA
RESIN
3
8
13
62
35
34
33
16
X2
X1
48
2
C
18 pF
18 pF
1
C
Q1
24.576 MHz
VIN
UIN
YIN
CVBS
SCL
SDA
RESOUTN
BLN
VS
CLK2
H1I1
CLK1
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
SDA 9206
UES10472
6.8 /
ABACUS
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