參數(shù)資料
型號: MT49H16M18C
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 41/44頁
文件大?。?/td> 1117K
代理商: MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
41
Absolute Maximum Ratings*
Storage Temperature . . . . . . . . . . . . . . . .-55°C to +150°C
I/O Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
Q + 0.3V
Voltage on V
EXT
Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . -0.3V to +2.8V
Voltage on V
DD
Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Voltage on V
DD
Q Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Junction Temperature**. . . . . . . . . . . . . . . . . . . . . . .110°C
*Stresses greater than those listed may cause per-
manent damage to the device. This is a stress rating
only, and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
**Junction temperature depends upon package
type, cycle time, loading, ambient temperature, and
airflow.
NOTE:
1. All voltages referenced to V
SS
(GND).
2. Typically the value of V
REF
is expect to be 0.5 x V
DD
Q of the transmitting device. V
REF
is expected to track variations in
V
DD
Q.
3. Peak-to-peak AC noise on V
REF
must not exceed ±2% V
REF
(dc).
4. Overshoot:
V
IH
(
AC
)
V
DD
+ 0.7V for t
t
CK/2.
Undershoot: V
IL
(
AC
)
-0.5V for t
t
CK/2.
During normal operation, V
DD
Q must not exceed V
DD
.
Control input signals may not have pulse widths less than
t
CK/2 or operate at frequencies exceeding
t
CK (MAX).
5. V
DD
Q can be set to a nominal 1.5V + 0.1V or 1.8V + 0.1V supply
6. I
OH
and I
OL
are defined as absolute values and are measured at V
DD
Q/2. I
OH
flows from the device, I
OL
flows into the
device.
7. If MRS bit A8 is 0, use RQ = 250
in the equation in lieu of presence of an external impedance matched resistor.
8. V
REF
is expected to equal V
DD
Q/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-
peak noise (non-common mode) on V
REF
may not exceed ±2% of the DC value. Thus, from V
DD
Q/2, V
REF
is allowed
±2%V
DD
Q/2 for DC error and an additional ±2%V
DD
Q/2 for AC noise. This measurement is to be taken at the nearest
V
REF
bypass capacitor.
9. V
TT
is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
10. On-die termination may be selected using mode register bit 9 (see Figure 10 on page 16). A resistance R
TT
from each
data input signal to the nearest V
TT
can be enabled. R
TT
= 150
(± 10%) at 70°C T
C
.
11. For V
OL
and V
OH
, refer to the Spice Model fro the RLDRAM II Command Driver.
Table 19:
(+0°C
T
C
+95°C; +1.7V
V
DD
+1.9V, unless otherwise noted)
DC Electrical Characteristics and Operating Conditions
DESCRIPTION
CONDITIONS
SYMBOL
V
EXT
V
DD
V
DD
Q
V
REF
V
TT
V
IH
V
IL
I
OH
MIN
2.38
1.7
1.4
MAX
2.63
1.9
Vdd
UNITS
V
V
V
V
V
V
V
mA
NOTES
1
1, 4
1, 4, 5
1–3, 8
9, 10
1, 4
1, 4
6, 7, 11
Supply Voltage
Supply Voltage
Isolated Output Buffer Supply
Reference Voltage
Termination Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Output High Current
0.49
X
V
DD
Q
0.95
X
V
REF
V
REF
+ 0.1
V
SS
Q - 0.3
(V
DD
Q/2) /
(1.15
X
RQ/5)
(V
DD
Q/2) /
(1.15
X
RQ/5)
-5
-5
-5
-5
0.51
X
V
DD
Q
1.05
X
V
REF
V
DD
Q + 0.3
V
REF
- 0.1
(V
DD
Q/2) /
(0.85
X
RQ/5)
(V
DD
Q/2) /
(0.85
X
RQ/5)
5
5
5
5
V
OH
= V
DD
Q/2
Output Low Current
V
OL
= V
DD
Q/2
I
OL
mA
6, 7, 11
Clock Input Leakage Current
Input Leakage Current
Output Leakage Current
Reference Voltage Current
0V
V
IN
V
DD
0V
V
IN
V
DD
0V
V
IN
V
DD
Q
I
LC
I
LI
I
LO
I
REF
μA
μA
μA
μA
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