參數(shù)資料
型號(hào)： MT49H16M18C
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁數(shù)： 19/44頁
文件大?。?/td> 1117K
代理商： MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
19
Figure 13: Write Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1
Figure 14: Write Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1
NOTE:
1. A/BAx: Address A of bank
x
WR: WRITE command
D
xy
: Data
y
to bank
x
RC: Row cycle time
WL: WRITE latency
2. Any free bank may be used in any given CMD. The sequence shown is only one example of a bank sequence.
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
ADDR
WL = 5
D
D0a
D1a
D0b
D1b
D2a
D2b
D3a
D3
WR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA4
A
BA5
A
BA6
A
BA7
WR
WR
WR
WR
WR
WR
WR
WR
DK#
DK
RC = 4
ADDR
BA
BA
A
BA
BA
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
WL = 5
D
D0a
D0c
D0b
D0d
D1a
D1b
D1c
D1
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
DON’T CARE
DK#
DK
RC = 4
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