參數(shù)資料
型號(hào)： MT49H16M18C
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁數(shù)： 32/44頁
文件大?。?/td> 1117K
代理商： MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
32
Address Mapping
The address mapping is described in Table 10 as a
function of data width and burst length.
NOTE:
1. X means “Don’t Care.”
2. Reserved for A20 expansion in multiplexed mode.
3. Reserved for A21 expansion in multiplexed mode.
Table 10:
Note 1
Address Mapping in Multiplexed Address Mode
DATA
WIDTH
x18
BURST
LENGTH
BL = 2
BALL
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
ADDRESSES
A0
2
A0
X
A0
X
A0
X
A0
A20
A0
X
A0
X
A3
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
3
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A8
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A9
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A10
A10
A19
A10
X
A10
X
A10
A19
A10
A19
A10
X
A13
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A18
A15
A18
A15
X
A15
A18
A15
A18
A15
A18
A15
BL = 4
BL = 8
x9
BL = 2
BL = 4
BL = 8
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