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參數(shù)資料
| 型號(hào)： | MT4C1004J |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 1 FPM DRAM(4 M x 1快速頁(yè)面模式動(dòng)態(tài)RAM) |
| 中文描述： | 4梅格× 1快速頁(yè)面模式的DRAM（四米× 1快速頁(yè)面模式動(dòng)態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | MT4C1004J |
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4 Meg x 1 FPM DRAM
D03.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
1
4 MEG x 1
FPM DRAM
OBSOLETE
DRAM
PIN ASSIGNMENT (Top View)
MT4C1004J
20/26-Pin SOJ
(DA-1)
FEATURES
1,024-cycle refresh distributed across 16ms
(MT4C1004J) or 128ms (MT4C1004J L only)
Industry-standard pinout, timing, functions and
packages
High-performance CMOS silicon-gate process
Single +5V
±
10% power supply
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional Extended
FAST PAGE MODE access cycle
OPTIONS
Timing
60ns access
MARKING
-6
Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
Refresh Rate
Standard 16ms period
Extended 128ms period
None
L
Part Number Example: MT4C1004JDJ-6 L
20/26-Pin TSOP
(DB-1)
KEY TIMING PARAMETERS
SPEED
-6
t
RC
110ns
t
RAC
60ns
t
PC
35ns
t
AA
30ns
t
CAC
15ns
t
RP
40ns
GENERAL DESCRIPTION
The MT4C1004J(L) is a randomly accessed, solid-state
memory containing 4,194,304 bits organized in a x1 configu-
ration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered 11
bits (A0-A10) at a time. RAS# is used to latch the first 11 bits
and CAS# the latter 11 bits. READ and WRITE cycles are
selected with the WE# input. A logic HIGH on WE# dictates
READ mode while a logic LOW on WE# dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of WE# or CAS#, whichever occurs last. If WE#
goes LOW prior to CAS# going LOW, the output pin
remains open (High-Z) until the next CAS# cycle. If WE#
goes LOW after data reaches the output pin, data-out (Q) is
activated and retains the selected cell data as long as CAS#
remains LOW (regardless of WE# or RAS#). This late WE#
pulse results in a READ WRITE cycle.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (A0-A10) page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RAS# followed by a column address strobed-
in by CAS#. CAS# may be toggled-in by holding RAS#
LOW and strobing-in different column addresses, thus
executing faster memory cycles. Returning RAS#
HIGH
terminates the FAST PAGE MODE operation.
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby
level. Also, the chip is preconditioned for the next cycle
during the RAS# HIGH time. Memory cell data is retained
in its correct state by maintaining power and executing any
RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#
ONLY, CBR, or HIDDEN) so that all 1,024 combinations of
RAS# addresses (A0-A9) are executed at least every 16ms
for the MT4C1004J and every 128ms for the MT4C1004J L,
regardless of sequence. The CBR and extended refresh
cycles will
invoke the internal refresh counter for automatic
RAS# addressing.
*Address not used for RAS#-ONLY REFRESH
Note:
The # symbol indicates signal is active LOW.
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
D
WE#
RAS#
NC
*A10
A0
A1
A2
A3
Vcc
Vss
Q
CAS#
NC
A9
A8
A7
A6
A5
A4
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
D
WE#
RAS#
NC
*A10
A0
A1
A2
A3
Vcc
Vss
Q
CAS#
NC
A9
A8
A7
A6
A5
A4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
| MT4C4001STG-8 | standard or self refresh |
| MT4C4001JDJ-6 | standard or self refresh |
| MT4C4001SDJ-8 | standard or self refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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