參數(shù)資料
型號(hào)： MT49H16M18C
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁(yè)數(shù)： 36/44頁(yè)
文件大?。?/td> 1117K
代理商： MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
36
TAP Registers
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
RLDRAM test circuitry. Only one register can be
selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the fall-
ing edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO ball, as shown in
Figure 39. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
Bypass Register
To save time when serially shifting data through reg-
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the RLDRAM with
minimal delay. The bypass register is set LOW (V
SS
)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the
input and bidirectional balls on the RLDRAM. Several
balls are also included in the scan register to reserved
balls. The RLDRAM has a 113-bit register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state.
The Boundary Scan Order tables (see page 40) show
the order in which the bits are connected. Each bit cor-
responds to one of the balls on the RLDRAM package.
The MSB of the register is connected to TDI, and the
LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the RLDRAM and
can be shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and
other information described in the Identification Reg-
ister Definitions table.
TAP Instruction Set
Overview
Many different instructions (28) are possible with
the eight-bit instruction register. All used combina-
tions are listed in Table 17, Instruction Codes, on
page 39. These six instructions are described in detail
below. The remaining instructions are reserved and
should not be used.
The TAP controller used in this RLDRAM is fully
compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to
the component package to be tested. Boundary-scan
register cells at output balls are used to apply a test
vector, while those at input balls capture test results.
Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary
scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output
driver is turned on and the PRELOAD data is driven
onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
HIGH-Z
The High-Z instruction causes the boundary scan
register to be connected between the TDI and TDO.
This places all RLDRAM outputs into a High-Z state.
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