參數(shù)資料
型號: MT49H16M18C
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 25/44頁
文件大?。?/td> 1117K
代理商: MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
25
Figure 23: READ/WRITE Interleave: BL = 4,
t
RC = 4, WL = 5, Configuration 1
Figure 24: READ/WRITE Interleave: BL = 4,
t
RC = 6, WL = 7, Configuration 2
NOTE:
A/BAx: Address A of bank
x
WR: WRITE command
D
xy
: Data
y
to bank
x
WL: WRITE latency
RD: READ command
Qxy: Data
y
from bank
x
RL: READ latency
t
RC: Row cycle time
ADDR
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
WL = 5
Q
Q0a
Q0c
Q0b
Q0d Q2a Q2b
Q2c
Q2d
RD
WR
RD
WR
RD
WR
RD
WR
RD
QKx#
QKx
RL = 4
WR
RD
Q0b
Q0a
Q0c
Q0d Q2a
D
D1a
D1c
D1b
D1d
D3a
D3b
D3c
D3d
D1a
9
10
t
RC = 4
D
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA1
A
BA2
DON’T CARE
UNDEFINED
DON’T CARE
UNDEFINED
ADDR
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
WL = 7
Q
Q0a
Q0c
Q0b
Q0d Q2a Q2b Q2c
Q2d
RD
WR
RD
WR
RD
WR
RD
WR
RD
QKx#
QKx
RL = 6
WR
RD
RD
Q4b
Q4a
Q4c Q4d Q0a Q0b Q0c
D
D1a
D1c
D1b
D1d D3a D3b
D3c
D3d D5a
9
10
t
RC = 6
D
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA0
A
BA1
A
BA2
A
BA3
A
A
BA4
BA2
12
Q0d
WR
RD
WR
RD
Q2a
D5c
D5d D1a
13
14
A
BA5
A
BA0
A
BA1
A
BA2
11
D1
相關(guān)PDF資料
PDF描述
MT49H16M18CFM-xx 288Mb SIO REDUCED LATENCY(RLDRAM II)
MT49H32M9C 288Mb SIO REDUCED LATENCY(RLDRAM II)
MT49H32M9CFM-xx 288Mb SIO REDUCED LATENCY(RLDRAM II)
MT4C1004J 4 Meg x 1 FPM DRAM(4 M x 1快速頁面模式動態(tài)RAM)
MT4C4001STG-6 standard or self refresh
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT49H16M18CBM-25 制造商:Micron Technology Inc 功能描述:
MT49H16M18CBM-25 TR 制造商:Micron Technology Inc 功能描述:16MX18 RLDRAM PLASTIC PBF FBGA 1.8V SEPARATE I/O 8 BANKS - Tape and Reel
MT49H16M18CBM-33 IT 制造商:Micron Technology Inc 功能描述: