![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/DS34T102GN-_datasheet_97090/DS34T102GN-_202.png)
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
202 of 366
Tx_SW_CAS_TS7_TS0 0x000+(port-1)*0x10
Bits
Data Element Name
R/W
Reset
Value
Description
[31:28]
TS7_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 7
[27:24]
TS6_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 6
[23:20]
TS5_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 5
[19:16]
TS4_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 4
[15:12]
TS3_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 3
[11:8]
TS2_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 2
[7:4]
TS1_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 1
[3:0]
TS0_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 0
Tx_SW_CAS_TS15_TS8 0x004+(port-1)*0x10
Bits
Data Element Name
R/W
Reset
Value
Description
[31:28]
TS15_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 15
[27:24]
TS14_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 14
[23:20]
TS13_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 13
[19:16]
TS12_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 12
[15:12]
TS11_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 11
[11:8]
TS10_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 10
[7:4]
TS9_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 9
[3:0]
TS8_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 8
Tx_SW_CAS_TS23_TS16 0x008+(port-1)*0x10
Bits
Data Element Name
R/W
Reset
Value
Description
[31:28]
TS23_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 23
[27:24]
TS22_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 22
[23:20]
TS21_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 21
[19:16]
TS20_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 20
[15:12]
TS19_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 19
[11:8]
TS18_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 18
[7:4]
TS17_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 17
[3:0]
TS16_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 16
Tx_SW_CAS_TS31_TS24 0x00C+(port-1)*0x10
Bits
Data Element Name
R/W
Reset
Value
Description
[31:28]
TS31_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 31
[27:24]
TS30_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 30
[23:20]
TS29_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 29
[19:16]
TS28_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 28
[15:12]
TS27_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 27
[11:8]
TS26_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 26
[7:4]
TS25_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 25
[3:0]
TS24_CAS_nibble
R/W
None
CAS signaling (ABCD) for timeslot 24