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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 55/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
55
At this point, the system waits endlessly unless the bus cycle terminates. The best method is to
connect the ACKOUT* of the last CD1865 in the chain to a bus-error input on the host. If there are
multiple CD1865s that are not cascaded, the ACKOUT* signals should be OR
’
ed together through
a gate or a PAL.
If an acknowledgment occurs and the value on the address bus does not match any of the Match
registers, the first CD1865 in the chain does not pass it along or assert DTACK* and the system
waits endlessly unless there is a bus time-out or other mechanism to detect this condition. In either
of these circumstances, the
‘
value
’
on the data bus is likely to be FFh because the bus is floating
(this is system dependent). To make a robust design, do not use FFh as a valid Global Service
Vector register (GSVR) value. If daisy chaining is not enabled, then the CD1865 returns a vector of
‘
00
’
for invalid acknowledgments.
6.4.1
Interfacing to 80X86-Family Processors
The Intel 80X86 family processors often use the 8259A as the interrupt controller, which supplies
its own vector during the INTA cycle. The easiest way to interface the CD1865 to an Intel
processor is by Mixed mode, as described in
Section 5.5
.
There is one
‘
bug
’
in the 8259A to be aware of. The 8259A can change the prioritizing of its eight
inputs, which can result in one of its acknowledge outputs going low briefly (~30 ns) if an input
changes at a certain time. This typically occurs if a higher-priority input to the 8259A asserts when
the 8259A is about to issue an acknowledge to a lower-priority device. If this occurs at the
beginning of a cycle, this brief pulse can cause the CD1865 (and other devices) to malfunction. Be
sure that this does not occur. See
Intel 8259A Data Sheet
for details.
6.4.2
Interfacing to 680X0-Family Processors
The 68000-family interface is quite straightforward. The three service request lines go through a
priority encoder to the 680X0 IPL inputs. The CD1865s ACKIN* pin is driven by a decoder.
When the 680X0 performs an Interrupt Acknowledge cycle, it drives its address lines A1, A2, and
A3 with a three-bit value indicating the level being serviced. The other address lines are set to a 1.
If the level being serviced corresponds to a level assigned to the CD1865, external decoding logic
should assert the CD1865 ACKIN* pin. The value on address lines A0 to A7 is programmed into
the , so the CD1865 recognizes the acknowledgment and proceeds as described in the Service
Request
Section 5.3.1
.
All CD1865 service requests can also be routed to a single interrupt level by using a Mixed-mode
interface, as described in
Section 5.5
.
6.4.3
Interfacing to the VME Bus
The CD1865 can be directly interfaced to the VME bus, and only requires a small amount of logic
to complete the interface. This is necessary because service request acknowledgment works
differently on the VME bus than on the CD1865. VME defines seven levels of interrupts; each
level can be shared among multiple VME cards. During an Interrupt Acknowledge cycle, the VME
bus provides three bits on the address bus, indicating the level being acknowledged (A1-A3). Each
VME card must pass along an interrupt on all levels it is not using but the CD1865 does not
automatically pass an interrupt acknowledgment.
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| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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