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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 138/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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CD1865
—
Intelligent Eight-Channel Communications Controller
138
Datasheet
t
20
ACKOUT* assert after CS* and DS* {RD*} active on register
acknowledge cycles with no match
25
17
t
21
DTACK* active pull-up time
18
NOTES:
1. Unless otherwise noted, all values are in nanoseconds (ns).
2. During read cycles, CS* and DS* {RD*} are gated together internally. This specification is with respect to whichever goes
active (low) last.
3. During read cycles, CS* and DS* {RD*} are gated together internally. This specification is with respect to whichever goes
inactive (high) last.
4. This specification is with respect to whichever goes inactive (high) last.
5. The values given is for 15-MHz operation. The time depends on system clock rate and the chosen DTACKDLY option. The
actual time in any case can be determined by the formula:
If DTACKDLY = 0, then the time is 1.5(Tclk) + 30 ns
If DTACKDLY = 1, then the time is 2.0(Tclk) + 35 ns
6. This specification is with respect to whichever of ACKIN* and DS* {RD*} goes active (low) last.
7. The data bus is three-stated immediately after removal of DS* {RD*}. The device is guaranteed to be off the bus by the
specified maximum time. The time can be as short as the minimum time. The hardware design should ensure that the data
has been read before DS* {RD*} is removed.
4.
In multiple CD1865 designs, the Interrupt Acknowledge cycle must be long enough to accommodate the ACKIN* to
ACKOUT* daisy-chain propagation delay from the first to the last CD1865. ACKIN* must remain low until after
DTACK
* asserts.
8. For Acknowledge cycles, this specification refers to ACKIN* instead of CS*.
9. During Interrupt Acknowledge cycles, ACKIN* is asserted instead of CS*; CS* should remain high. Note that ACKIN* timing is
not always the same as CS*.
10.During acknowledge cycles, addresses must propagate through the Service Match Registers. If a service request is pending
on this CD1865, the match must finish before ACKIN* asserts. This is ensured by the specifications.
11.This specification is with respect to ACKIN* only.
12.This specification refers to one of Receive, Transfer, or Modem Service Request Outputs (RREQ*, TREQ*, MREQ*).
13.This specification is with respect to DS*. CS* and R/W* must be high before the assertion of DS* to avoid the possibility of the
CD1865 misinterpreting the cycle as a read or write.
14.This is the time required to reassert a service request if the internal conditions of the CD1865 are such that the request
should be asserted.
15.This specification refers to one of Receive, Transfer, or Modem Service Request Outputs (RREQ*, TREQ*, MREQ*).
16.The data bus is guaranteed to become active after DS* {RD*} low and before data is valid.
17.This is the time for ACKOUT* to assert on register acknowledge cycles. ACKOUT* asserts if the part determines the
acknowledgment is not intended for that part. If ACKOUT* asserts, the part does not drive the data bus or assert DTACK*.
These functions are left to a device further down the daisy chain that accepts the acknowledge cycle.
18.DTACK* sources current (drives
‘
high
’
) until the voltage on the DTACK* line reaches 1.5V. At that time, DTACK* switches to
an
‘
open-drain
’
(high-impedance) state.
Table 11. Unclocked Timings
(Sheet 2 of 2)
Number
Description
MIN1
MAX1
Notes
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相關(guān)代理商/技術(shù)參數(shù) |
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| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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