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參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 27/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
27
If AutoPri is not being used, the CD1865 needs to be informed which one of the three possible
pending requests the host wants to acknowledge. There are two different ways CD1865 can be
informed of this
—
hardware and software.
The hardware method is based on the value in the address bus. The CD1865 determines the type of
request being acknowledged by the value placed in the address bus during the acknowledge cycle.
This is the method used by Motorola
-family processors. The host places the level of interrupt
being serviced on the low-order address bits during an interrupt acknowledgment cycle. When the
host performs a Service Acknowledge cycle, the CD1865 compares the value on the address bus
with the three unique values stored in three internal registers
—
the . These values are set by the
user at system initialization. A match occurs on only one of these registers, and this informs the
CD1865 of the type of request being acknowledged.
In most circumstances the address bus should not have a value that does not match one of the three
values during an acknowledgment cycle. This causes the CD1865 to not recognize that any bus
cycle is occurring, and it does not assert DTACK*, or terminate the cycle, or take any other action.
Doing this does not affect the CD1865, but the system must have some other provision to terminate
the bus cycle. If, for example, the CD1865 shares an interrupt level with another device, different
values on the address bus should be used to control responses to an acknowledgment, but the bus
cycle should terminate in a usable way.
Service acknowledgments can also be performed by software. The host simply reads one of three
Request Acknowledge registers, and the CD1865 performs as if a hardware service acknowledge
cycle is executed.
Regardless of the method of acknowledgment used, within the CD1865, each service request state
machine makes the following determination: if it has an internal service request pending, and there
is a service acknowledge of the same type, it asserts its internal-acknowledge-accepted signal back
to the Service Request Controller logic, negates the Service Request Output pin, and holds its
acknowledge-out daisy chain in a negated state. It also drives the value in the Global Vector
register (GVR) onto the data bus, for the host to read as part of the Service Acknowledge cycle.
The GVR value placed on the bus during the Service Acknowledge cycle serves two purposes. The
least-significant three bits of GVR indicate which of the four types of service requests are
occurring. The upper-five bits are user-defined and serve to identify, in daisy-chained CD1865
systems, which of the multiple CD1865s is active.
If the service request state machine does not have a service request pending, and there is a software
acknowledgment or address bus match, it passes the service acknowledgment down the chain by
asserting ACKOUT*. If there is no match, the state machine remains idle.
If a service request is pending and the Receive Service Request is to be handled, the CD1865 is
notified because the three have different values in them; therefore, only one match (receive
service, in this case) occurred. The internal grant from the service request state machine causes the
receive service type code and active channel number (previously stored at the time the request is
posted by the CD1865 processor) to be pushed onto the service request stack. This automatically
causes the FIFO pointers to be set up for the active channel, with no host intervention.
The host, at this point, has all the information needed to handle the service request. It determines
the exact type of service being requested (Transmit, Receive Good Data, Receive Exception, or
Modem signal change) and which of the multiple CD1865s is requesting service. It gets the
channel number by reading the Global Channel register (GCR) and then proceeds to service the
request. At the completion of the service, the host performs a dummy write to the CD1865 End Of
register (), that causes the CD1865 to exit its internal service request state by popping the service
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| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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