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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 130/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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CD1865
—
Intelligent Eight-Channel Communications Controller
130
Datasheet
t
26
DTACK* negate after DS* {RD* or WR*} negation
10
t
27
ACKOUT* assert after CS* and DS* active on register acknowledge cycle
with no match
22
13
t
28
DTACK* active pull-up time
14
t
29
ACKOUT* high after end of cycle
22
NOTES:
1. Unless otherwise noted, all values are in nanoseconds (ns).
2. The reference to DS* and CS* refers to whichever one goes active last; that is, both signals must meet the setup time
requirement.
3. Enabling the Register Acknowledge (
‘
regack
’
) feature changes the timing somewhat, even on cycles where
‘
regack
’
is not
being used.
4. Calculated value; guaranteed by design, but not tested.
5. For Motorola-style interface, refers to R/W*.For Intel-style interface, refers to RD* or WR* (whichever is inactive for that
cycle).
6. A cycle must positively end before another begins; that is, control signals shall return to states such that no cycle is pending
or active.
7. Guaranteed by design, but not tested.
8. During Register Based Acknowledge cycles, these signals must be held in the correct state until valid data is presented by
the device, as indicated by DTACK* going active. Note that in daisy-chain applications, the response from the chain may be
quite long due to the ACKIN*-ACKOUT* propagation delay required for the actual interrupting device to receive the select
(ACKIN*). Waiting for the active DTACK* from the chain eliminates any timing problems relating to these parameters.
9. ACKIN* must be low for at least one clock period plus setup and hold times if there is only one CD1865 in the daisy chain. If
there is more than one CD1865 in a daisy chain, ACKIN* must be low until it has rippled all the way down the chain.
10.When using the clock out (CKOUT) of one CD1865 to drive subsequent CD1865s (such as in daisy-chain environments),
CKOUT is skewed (delayed) by 3 ns from the internal clock. Therefore, on subsequent CD1865s, setup times are improved
by 3 ns and hold times are derated by 3 ns.
11.For clock periods greater than 100 ns (10 MHz or less clock), rise and fall time may be 5 ns maximum.
12.Greater than a
‘
0
’
by design, but not tested.
13.This is the time for ACKOUT* to assert on register acknowledge cycles. ACKOUT* asserts if the device determines the
acknowledgment is not intended for that part. If ACKOUT* asserts, the device does not drive the data bus or assert DTACK*.
These functions are left to a device further down the daisy chain that accepts the acknowledge cycle.
14.DTACK* sources current (drives
‘
high
’
) until the voltage on the DTACK* line is approximately 1.5 volts. Then DTACK* goes to
an
‘
open-drain
’
(high-impedance) state.
Figure 29. Clocked Bus Interface Reset
Table 10. Clocked Timings
(Sheet 2 of 2)
Number in
Figures
Description
MIN (1)
MAX (1)
Notes
V
CC
CLK
RESET*
t
18
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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