CD1865
—
Intelligent Eight-Channel Communications Controller
102
Datasheet
Within any one CD1865, the three Match registers must have unique values. In multiple CD1865
designs where service acknowledgments are cascaded, all Match registers of the same type (for
example, Receive) must have the same value.
In designs using register-based service acknowledgments (RRAR, TRAR, and MRAR), the
addresses of these registers must be placed in the equivalent Match register so that contains $77.
9.2.2.6
Global Vector Register
Register Name:
Register Description: Global Service Vector Register
Default Value: FF
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: $40
Intel Hex Address: $80
Motorola Hex Address: $81
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary Value
IT2
IT1
IT0
Bit
Description
Bits 7:3
These bits are user-defined. However, in a multiple-device design, these five bits must have a unique value in
each CD1865 to identify which CD1865 is returning a vector during service acknowledgments. When writing
to this register, write eight bits at once; the CD1865 modifies the low-three bits automatically. Note that if this
register is read in a normal manner, the original eight bits are read and the modified bits from the last
acknowledgment cycle is not preserved.
Bits 2:0
These three bits indicate the group/type of service request occurring. These bit are supplied by the CD1865
during an acknowledgment cycle.
NOTE:
* This code is returned by the CD1865 only when RegAckEn is set, and DaisyEn is not set. In this
condition, the CD1865 must provide a vector when acknowledged. If the CD1865 receives an
acknowledgment for which it does not have a request pending, it returns
‘
000
’
.
IT2
IT1
IT0
Value
Group/Type
0
0
0
0
No Request Pending*
0
0
1
1
Modem Signal Change Service Request
0
1
0
2
Transmit Data Service Request
0
1
1
3
Receive Good Data Service Request
1
0
0
4
Reserved
1
0
1
5
Reserved
1
1
0
6
Reserved
1
1
1
7
Receive Exception Service Request