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參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 37/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
37
This method is called
‘
Software Polled
’
. Polling is often used in situations where the host
system is primarily dedicated to servicing the serial channels and has few other tasks to
perform. It is usually better when the host CPU has a long interrupt context switch time. In this
method, the host periodically checks the CD1865s to determine if any service requests are
pending. If they are, the host acknowledges them in software and proceeds with the service.
One of the advantages of the CD1865 is that it allows the use of any of the above techniques, or a
combination. Such a combination is referred to as
‘
Mixed-mode operation
’
. In a typical mixed-
mode design, normal interrupts are used to signal to the host that service is required. After the host
enters its interrupt service routine, it services the CD1865 that generated the service request. Then
the host polls the CD1865s to determine if more channels require service. If the host finds a
channel requiring service, it handles it in the usual manner, and then proceeds to poll for more
service requests. This process continues until all CD1865s are handled. Because the host is not
exiting and re-entering its own interrupt context each time, much host CPU time is saved, resulting
in even faster overall performance.
The Advantage of a mixed-mode design is that the software has complete control of whether to be
fully interrupt driven or to poll in certain circumstances. A mixed-mode design is recommended to
tune a system for optimum performance.
A CD1865 evaluation board can be employed to analyze CD1865 performance and evaluate
different software implementations. Intel testing (in an AT-compatible
’
386 machine) found that a
mixed-mode system provided the highest overall throughput with minimum host CPU loading.
This is generally found to be the case with host processors that have relatively long interrupt
response times, such as the Intel
’
386.
5.5.1
Method 1a
—
Full Interrupt
–
Type A, Three-Level Interrupt
with Three-Level Acknowledge
This method is illustrated in
Figure 8
. It is best-suited for 680X0-family processors. The three
CD1865 service request lines are connected to the Interrupt Priority Encoder. When the host
performs an interrupt acknowledgment cycle, the CD1865 responds with its vector. The host uses
this vector to jump directly to the appropriate service routine. Other methods can also be used with
a 680X0-based system.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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