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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 85/188頁(yè) |
| 文件大小： | 1120K |
| 代理商： | SYM53C810A |
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Operating Registers
SYM53C810A Data Manual
5-27
for table indirect calculations, and the address
pointer for a call or return instruction, respec-
tively. T his bit is intended for manufacturing
diagnostics only and should not be set during
normal operations.
Bit 3
MPE E (Master Parity E rror E nable)
Setting this bit enables parity checking during
master data phases. A parity error during a bus
master read is detected by the SYM53C810A.
A parity error during a bus master write is
detected by the target, and the SYM53C810A
is informed of the error by the PERR/ pin
being asserted by the target. When this bit is
reset, the SYM53C810A will not interrupt if a
master parity error occurs. T his bit is reset at
power up.
Bits 2-0 FBL2-FBL0 (FIFO byte control)
T hese bits steer the contents of the CT EST 6
register to the appropriate byte lane of the 32-
bit DMA FIFO. If the FBL2 bit is set, then
FBL1 and FBL0 determine which of four byte
lanes can be read or written. When cleared, the
byte lane read or written is determined by the
current contents of the DNAD and DBC regis-
ters. Each of the four bytes that make up the
32-bit DMA FIFO can be accessed by writing
these bits to the proper value. For normal
operation, FBL2 must equal zero.
Register 22 (A2)
Chip Test Five (CT EST 5)
Read/Write
Bit 7
ADCK (Clock address incrementor)
Setting this bit increments the address pointer
contained in the DNAD register. T he DNAD
register is incremented based on the DNAD
contents and the current DBC value. T his bit
automatically clears itself after incrementing
the DNAD register.
Bit 6
BBCK (Clock byte counter)
Setting this bit decrements the byte count con-
tained in the 24-bit DBC register. It is decre-
mented based on the DBC contents and the
current DNAD value. T his bit automatically
clears itself after decrementing the DBC regis-
ter.
Bit 5
Reserved
Bit 4
MASR (Master control for set or
reset pulses)
T his bit controls the operation of bit 3. When
this bit is set, bit 3 asserts the corresponding
signals. When this bit is reset, bit 3 deasserts
the corresponding signals. T his bit and bit 3
should not be changed in the same write cycle.
Bit 3
DDIR (DMA direction)
Setting this bit either asserts or deasserts the
internal DMA Write (DMAWR) direction sig-
nal depending on the current status of the
MASR bit in this register. Asserting the
DMAWR signal indicates that data will be
transferred from the SCSI bus to the host bus.
Deasserting the DMAWR signal transfers data
from the host bus to the SCSI bus.
Bits 2-0 Reserved
FBL2
FBL1
FBL0
DMA FIFO
Byte lane
Pins
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disabled
0
1
2
3
n/a
D(7-0)
D(15-8)
D(23-16)
D(31-24)
ADCK
7
BBCK
6
RES
5
MASR
4
DDIR
3
RES
2
RES
1
RES
0
Default>>>
0
0
X
0
0
X
X
X
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