- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385894 > SYM53C810A (LSI Corporation) PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 75/188頁(yè) |
| 文件大小： | 1120K |
| 代理商： | SYM53C810A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)
Operating Registers
SYM53C810A Data Manual
5-17
Bit 4
ABRT (Aborted)
T his bit is set when an abort condition occurs.
An abort condition occurs when a software
abort command is issued by setting bit 7 of the
ISTAT register.
Bit 3
SSI (Single step interrupt)
If the Single-Step Mode bit in the DCNT L
register is set, this bit will be set and an inter-
rupt generated after successful execution of
each SCRIPT S instruction.
Bit 2
SIR (SCRIPT S interrupt
instruction received)
T his status bit is set whenever an Interrupt
instruction is evaluated as true.
Bit 1
Reserved
Bit 0
IID (Illegal instruction detected)
T his status bit is set any time an illegal instruc-
tion is detected, whether the SYM53C810A is
operating in single-step mode or automatically
executing SCSI SCRIPT S. T his bit will also be
set if one of the following conditions occurs:
1. If the SYM53C810A is executing a Wait
Disconnect instruction and the SCSI REQ
line is asserted without a disconnect
occurring.
2. If a Move, Chained Move, or Memory
Move command with a byte count of zero
is fetched.
3. If a Load/Store memory address maps back
into chip register space.
Register 0D (8D)
SCSI Status Zero (SSTAT 0)
Read Only
Bit 7
ILF (SIDL full)
T his bit is set when the SCSI Input Data Latch
register (SIDL) contains data. Data is trans-
ferred from the SCSI bus to the SCSI Input
Data Latch register before being sent to the
DMA FIFO and then to the host bus. T he
SIDL register contains SCSI data received
asynchronously. Synchronous data received
does not flow through this register.
Bit 6
ORF (SODR full)
T his bit is set when the SCSI Output Data
Register (SODR, a hidden buffer register
which is not accessible) contains data. T he
SODR register is used by the SCSI logic as a
second storage register when sending data syn-
chronously. It cannot be read or written by the
user. T his bit can be used to determine how
many bytes reside in the chip when an error
occurs.
Bit 5
OLF (SODL full)
T his bit is set when SCSI Output Data Latch
(SODL) contains data. T he SODL register is
the interface between the DMA logic and the
SCSI bus. In synchronous mode, data is trans-
ferred from the host bus to the SODL register,
and then to the SCSI Output Data Register
(SODR, a hidden buffer register which is not
accessible) before being sent to the SCSI bus.
In asynchronous mode, data is transferred
from the host bus to the SODL register, and
then to the SCSI bus. T he SODR buffer regis-
ter is not used for asynchronous transfers. T his
bit can be used to determine how many bytes
reside in the chip when an error occurs.
ILF
7
ORF
6
OLF
5
AIP
4
LOA
3
WOA
2
RST
1
SDP0/
0
Default>>>
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SYM53C825A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C825AE | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C860 | Single-Chip High-Performance PCI-Ultra SCSI (Fast-20) I/O Processor(單片、高性能PCI-超級(jí)SCSI (Fast-20) I/O 處理器) |
| SYM53C875 | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| SYM53C875E | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C885 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| SYM53C896 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| SYM-63LH+ | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:Frequency Mixer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。