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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 110/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Instruction Set of the I/O Processor
SCSI SCRIPTS
6-2
SYM53C810A Data Manual
Sample Operation
T he following example describes execution of a
SCRIPT S instruction. T his sample operation is for
a Block Move instruction. Figure 6-1 illustrates a
SCRIPT S Initiator Write operation, which uses
several Block Move instructions.
1. T he host CPU, through programmed I/O,
gives the DMA SCRIPT S Pointer (DSP)
register (in the Operating Register file) the
starting address in main memory that points to
a SCSI SCRIPT S program for execution.
2. Loading the DSP register causes the
SYM53C810A to request use of the PCI bus
to fetch its first instruction from main memory
at the address just loaded.
3. T he SYM53C810A typically fetches two
dwords (64 bits) and decodes the high order
byte of the first dword as a SCRIPT S
instruction. If the instruction is a Block Move,
the lower three bytes of the first dword are
stored and interpreted as the number of bytes
to be moved. T he second dword is stored and
interpreted as the 32-bit beginning address in
main memory to which the move is directed.
4. For a SCSI send operation, the SYM53C810A
waits until there is enough space in the DMA
FIFO to transfer a programmable size block of
data. For a SCSI receive operation, it waits
until enough data is collected in the DMA
FIFO for transfer to memory.
5. SYM53C810A requests use of the PCI bus
again, this time for data transfers.
6. When the SYM53C810A is again granted the
PCI bus, it will execute (as a bus master) a
burst transfer (programmable size) of data,
decrement the internally stored remaining byte
count, increment the address pointer, and then
release the PCI bus. T he SYM53C810A stays
off the PCI bus until the FIFO can again hold
(for a write) or has collected (for a read)
enough data to repeat the process.
T he process repeats until the internally stored byte
count has reached zero. T he SYM53C810A
releases the PCI bus and then requests use of the
PCI bus again for another SCRIPT S instruction
fetch cycle, using the incremented stored address
maintained in the DMA SCRIPT S Pointer regis-
ter. Execution of SCRIPT S instructions continues
until an error condition occurs or an interrupt
SCRIPT S instruction is received. At this point, the
SYM53C810A interrupts the host CPU and waits
for further servicing by the host system. It can exe-
cute independent Block Move instructions, speci-
fying new byte counts and starting locations in
main memory. In this manner, the SYM53C810A
performs scatter/gather operations on data without
requiring help from the host program, generating a
host interrupt, or requiring an external DMA con-
troller to be programmed.
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