
PCI Functional Description
PCI Cache Mode
SYM53C810A Data Manual
3-5
Burst Size Selection
T he Read Multiple command reads in multiple
cache lines of data in a single bus ownership. T he
number of cache lines to be read is determined by
the DMODE burst size bits. In other words, the
chip will switch its normal operating burst size to
reflect the DMODE burst size settings for the
Read Multiple command. For example, if the
cache line size is 4, and the DMODE burst size is
16, the chip will switch the current burst size from
4 to 16, and issue a Read Multiple. After the trans-
fer, the chip will then switch the burst size back to
the normal operating burst size of 4.
Read Multiple with Read Line E nabled
When both the Read Multiple and Read Line
modes have been enabled, the Read Line com-
mand will not be issued if the above conditions are
met. Instead, a Read Multiple command will be
issued, even though the conditions for Read Line
have been met.
If the Read Multiple mode is enabled and the Read
Line mode has been disabled, Read Multiple com-
mands will still be issued if the Read Multiple con-
ditions are met.
Unsupported PCI
Commands
T he SYM53C810A does not respond to reserved
commands, special cycle, dual address cycle, or
interrupt acknowledge commands as a slave. It will
never generate these commands as a master.
Table 3-1: PCI Bus Commands and E ncoding Types
C_BE(3-0)
Command Type
Supported as Master
Supported as Slave
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read Cycle
I/O Write Cycle
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
No
No
Yes
Yes
No
No
Yes
Yes
n/a
n/a
Yes
Yes
Yes
Yes
n/a
n/a
No
No
Yes
No
Yes
Yes
Yes
Yes
No (defaults to 0110)
No
No (defaults to 0110)
No (defaults to 0111)