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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 55/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Signal Descriptions
SYM53C810A Data Manual
4-5
Table 4-4: Interface Control Pins
Symbol
Pin No.
Type
Description
FRAME/
11
S/T /S
Cycle Frame.
Cycle Frame is driven by the current master to indi-
cate the beginning and duration of an access. FRAME/ is asserted
to indicate a bus transaction is beginning. While FRAME/ is
asserted, data transfers continue. When FRAME/ is deasserted, the
transaction is in the final data phase or the bus is idle.
Target Ready.
Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the transac-
tion. T RDY/ is used with IRDY/. A data phase is completed on any
clock when both T RDY/ and IRDY/ are sampled asserted. During a
read, T RDY/ indicates that valid data is present on AD(31-0). Dur-
ing a write, it indicates the target is prepared to accept data. Wait
cycles are inserted until both IRDY/ and T RDY/ are asserted
together.
Initiator Ready.
Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the transac-
tion. T his signal is used with T RDY/. A data phase is completed on
any clock when both IRDY/ and T RDY/ are sampled asserted. Dur-
ing a write, IRDY/ indicates that valid data is present on AD(31-0).
During a read, it indicates the master is prepared to accept data.
Wait cycles are inserted until both IRDY/ and T RDY/ are asserted
together.
Stop.
Stop indicates that the selected target is requesting the master
to stop the current transaction.
Device Select.
Device Select indicates that the driving device has
decoded its address as the target of the current access. As an input,
it indicates to a master whether any device on the bus has been
selected.
Initialization Device Select.
Initialization Device Select is used as a
chip select in place of the upper 24 address lines during configura-
tion read and write transactions.
T RDY/
14
S/T /S
IRDY/
12
S/T /S
ST OP/
17
S/T /S
DEVSEL/
15
S/T /S
IDSEL
97
I
Table 4-5: Arbitration Pins
Symbol
Pin No.
Type
Description
REQ/
83
O
Request.
Request indicates to the arbiter that this agent desires to
use the PCI bus. T his is a point-to-point signal. Every master has its
own REQ/.
Grant.
Grant indicates to the agent that access to the PCI bus has
been granted. T his is a point-to-point signal. Every master has its
own GNT /.
GNT /
82
I
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