參數(shù)資料
型號(hào): SYM53C810A
廠商: LSI Corporation
英文描述: PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述: 的PCI -的SCSI I / O處理器(個(gè)PCI -的SCSI的I / O接口處理器)
文件頁(yè)數(shù): 63/188頁(yè)
文件大小: 1120K
代理商: SYM53C810A
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Operating Registers
SYM53C810A Data Manual
5-5
Register 00 (80)
SCSI Control Zero (SCNT L0)
Read/Write
Bit 7
ARB1 (Arbitration mode bit 1)
Bit 6
ARB0 (Arbitration mode bit 0)
Simple Arbitration
1. T he SYM53C810A waits for a bus free
condition to occur.
2. It asserts SBSY/ and its SCSI ID
(contained in the SCID register) onto the
SCSI bus. If the SSEL/ signal is asserted by
another SCSI device, the SYM53C810A
will deassert SBSY/, deassert its ID and set
the Lost Arbitration bit (bit 3) in the
SSTAT 0 register.
3. After an arbitration delay, the CPU should
read the SBDL register to check if a higher
priority SCSI ID is present. If no higher
priority ID bit is set, and the Lost
Arbitration bit is not set, the
SYM53C810A has won arbitration.
4. Once the SYM53C810A has won
arbitration, SSEL/ must be asserted via the
SOCL for a bus clear plus a bus settle delay
(1.2
μ
s) before a low level selection can be
performed.
Full Arbitration, Selection/Reselection
1. T he SYM53C810A waits for a bus free
condition.
2. It asserts SBSY/ and its SCSI ID (stored in
the SCID register) onto the SCSI bus.
3. If the SSEL/ signal is asserted by another
SCSI device or if the SYM53C810A
detects a higher priority ID, the
SYM53C810A will deassert BSY, deassert
its ID, and wait until the next bus free state
to try arbitration again.
4. T he SYM53C810A repeats arbitration
until it wins control of the SCSI bus. When
it has won, the Won Arbitration bit is set in
the SSTAT 0 register, bit 2.
5. T he SYM53C810A performs selection by
asserting the following onto the SCSI bus:
SSEL/, the target’s ID (stored in the SDID
register), and the SYM53C810A’s ID
(stored in the SCID register).
6. After a selection is complete, the Function
Complete bit is set in the SIST 0 register,
bit 6.
7. If a selection time-out occurs, the Selection
T ime-Out bit is set in the SIST 1 register,
bit 2.
Bit 5
START (Start sequence)
When this bit is set, the SYM53C810A will
start the arbitration sequence indicated by the
Arbitration Mode bits. T he Start Sequence bit
is accessed directly in low-level mode; during
SCSI SCRIPT S operations, this bit is con-
trolled by the SCRIPT S processor. An arbitra-
tion sequence should not be started if the
connected (CON) bit in the SCNT L1 register,
bit 4, indicates that the SYM53C810A is
already connected to the SCSI bus. T his bit is
automatically cleared when the arbitration
sequence is complete. If a sequence is aborted,
bit 4 in the SCNT L1 register should be
checked to verify that the SYM53C810A did
not connect to the SCSI bus.
ARB1
7
ARB0
6
START
5
WATN
4
EPC
3
RES
2
AAP
1
TRG
0
Default>>>
1
1
0
0
0
X
0
0
ARB1
ARB0
Arbitration Mode
0
0
1
1
0
1
0
1
Simple arbitration
Reserved
Reserved
Full arbitration, selection/reselection
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