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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 36/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Functional Description
Interrupt Handling
2-14
SYM53C810A Data Manual
SIE N0 and SIE N1
T he SIEN0 and SIEN1 registers are the interrupt
enable registers for the SCSI interrupts in SIST 0
and SIST 1.
DIE N
T he DIEN register is the interrupt enable register
for DMA interrupts in DSTAT.
DCNT L
When bit 1 in this register is set, the IRQ/ pin will
not be asserted when an interrupt condition
occurs. T he interrupt is not lost or ignored, but
merely masked at the pin. Clearing this bit when
an interrupt is pending will immediately cause the
IRQ/ pin to assert. As with any register other than
ISTAT, this register cannot be accessed except by a
SCRIPT S instruction during SCRIPT S execution.
Fatal vs. Non-Fatal
Interrupts
A fatal interrupt, as the name implies, always
causes SCRIPT S to stop running. All non-fatal
interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. For
more information on interrupt masking, see the
discussion on masking later in this section. All
DMA interrupts (indicated by the DIP bit in
ISTAT and one or more bits in DSTAT being set)
are fatal.
Some SCSI interrupts (indicated by the SIP bit in
the ISTAT and one or more bits in SIST 0 or
SIST 1 being set) are non-fatal. When the
SYM53C810A is operating in initiator role, only
the Function Complete (CMP), Selected (SEL),
Reselected (RSL), General Purpose T imer Expired
(GEN), and Handshake to Handshake T imer
Expired (HT H) interrupts are non-fatal. When
operating in target role CMP, SEL, RSL, Target
mode: SAT N/ active (M/A), GEN, and HT H are
non-fatal. Refer to the description for the Disable
Halt on a Parity Error or SAT N/ active (Target
Mode Only) (DHP) bit in the SCNT L1 register to
configure the chip’s behavior when the SAT N/
interrupt is enabled during target role operation.
T he Interrupt on the Fly interrupt is also non-
fatal, since SCRIPT S can continue when it occurs.
T he reason for non-fatal interrupts is to prevent
SCRIPT S from stopping when an interrupt occurs
that does not require service from the CPU. T his
prevents an interrupt when arbitration is complete
(CMP set), when the SYM53C810A has been
selected or reselected (SEL or RSL set), when the
initiator has asserted AT N (target mode: SAT N/
active), or when the General Purpose or Hand-
shake to Handshake timers expire. T hese inter-
rupts do not require CPU intervention during
high-level SCRIPT S operation.
Masking
Masking an interrupt means disabling or ignoring
that interrupt. Interrupts can be masked by clear-
ing bits in the SIEN0 and SIEN1 (for SCSI inter-
rupts) registers or the DIEN (for DMA interrupts)
register. How the chip will respond to masked
interrupts depends on: whether polling or hard-
ware interrupts are being used; whether the inter-
rupt is fatal or non-fatal; and whether the chip is
operating in initiator or target role.
If a non-fatal interrupt is masked and that condi-
tion occurs, SCRIPT S will not stop, the appropri-
ate bit in the SIST 0 or SIST 1 will still be set, the
SIP bit in the ISTAT will not be set, and the IRQ/
pin will not be asserted. See the section on non-
fatal vs. fatal interrupts for a list of the non-fatal
interrupts.
If a fatal interrupt is masked and that condition
occurs, then SCRIPT S will still stop, the appropri-
ate bit in the DSTAT, SIST 0, or SIST 1 register
will be set, and the SIP or DIP bits in the ISTAT
will be set, but the IRQ/ pin will not be asserted.
When the chip is initialized, enable all fatal inter-
rupts if you are using hardware interrupts. If a fatal
interrupt is disabled and that interrupt condition
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