III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33T01 FUNCTION PART
EPSON
B-III-10-25
PP0L2–PP0L0:
Port input 0 interrupt level (D[2:0]) / Port input 0/1 interrupt priority register (0x40260)
PP1L2–PP1L0:
Port input 1 interrupt level (D[6:4]) / Port input 0/1 interrupt priority register (0x40260)
PP2L2–PP2L0:
Port input 2 interrupt level (D[2:0]) / Port input 2/3 interrupt priority register (0x40261)
PP3L2–PP3L0:
Port input 3 interrupt level (D[6:4]) / Port input 2/3 interrupt priority register (0x40261)
PP4L2–PP4L0:
Port input 4 interrupt level (D[2:0]) / Port input 4/5 interrupt priority register (0x4026C)
PP5L2–PP5L0:
Port input 5 interrupt level (D[6:4]) / Port input 4/5 interrupt priority register (0x4026C)
PP6L2–PP6L0:
Port input 6 interrupt level (D[2:0]) / Port input 6/7 interrupt priority register (0x4026D)
PP7L2–PP7L0:
Port input 7 interrupt level (D[6:4]) / Port input 6/7 interrupt priority register (0x4026D)
PP8L2–PP8L0:
Port input 8 interrupt level (D[2:0]) / Port input 8/9 interrupt priority register (0x402A0)
PP9L2–PP9L0:
Port input 9 interrupt level (D[6:4]) / Port input 8/9 interrupt priority register (0x402A0)
PP10L2–PP10L0: Port input 10 interrupt level (D[2:0]) / Port input 10/11 interrupt priority register (0x402A1)
PP11L2–PP11L0: Port input 11 interrupt level (D[6:4]) / Port input 10/11 interrupt priority register (0x402A1)
PP12L2–PP12L0: Port input 12 interrupt level (D[2:0]) / Port input 12/13 interrupt priority register (0x402A2)
PP13L2–PP13L0: Port input 13 interrupt level (D[6:4]) / Port input 12/13 interrupt priority register (0x402A2)
PP14L2–PP14L0: Port input 14 interrupt level (D[2:0]) / Port input 14/15 interrupt priority register (0x402A3)
PP15L2–PP15L0: Port input 15 interrupt level (D[6:4]) / Port input 14/15 interrupt priority register (0x402A3)
PK0L2–PK0L0:
Key input 0 interrupt level (D[2:0]) / Key input interrupt priority register (0x40262)
PK1L2–PK1L0:
Key input 1 interrupt level (D[6:4]) / Key input interrupt priority register (0x40262)
Sets the priority level of the input interrupt.
PPxL and PKxL are interrupt priority registers corresponding to each port-input interrupt and key-input interrupt,
respectively.
The priority level can be set for each interrupt group in the range of 0 to 7.
At initial reset, these registers becomes indeterminate.
EP3–EP0:
ort input 3–0 interrupt enable (D[3:0]) / Key input, port input 0–3 interrupt enable register (0x40270)
EP7–EP4:
Port input 7–4 interrupt enable
(D[5:2]) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277)
EP15-EP8: Port input 15–8 interrupt enable (D[7:0]) / Port input interrupt enable register (0x402A6)
EK1, EK0: Key input 1, 0 interrupt enable (D[5:4]) / Key input, port input 0–3 interrupt enable register (0x40270)
Enables or disables the generation of an interrupt to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
EP and EK are interrupt enable bits corresponding to the port-input interrupt and the key-input interrupt,
respectively. Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are
disabled.
At initial reset, these bits are set to "0" (interrupt disabled).
FP3–FP0: Port input 3–0 interrupt factor flag (D[3:0]) / Key input, port input 0–3 interrupt factor flag register
(0x40280)
FP7–FP4: Port input 7–4 interrupt factor flag (D[5:2]) / Port input 4–7, clock timer, A/D interrupt factor
flag register (0x40287)
FP15–FP8: Port input 15–8 interrupt factor flag (D[7:0]) / Port input interrupt factor flag register (0x402A9)
FK1, FK0:
Key input 1, 0 interrupt factor flag (D[5:4]) / Key input, port input 0–3 interrupt factor flag
register (0x40280)
Indicates the status of an input interrupt factor generated.
When read
Read "1": Interrupt factor has occurred
Read "0": No interrupt factor has occurred