II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-22
EPSON
S1C33T01 FUNCTION PART
Exxx: Interrupt enable register
Enable or disable interrupt generation to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are
set to "0".
For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt
enable register bit must be set for interrupt enable.
When initially reset, this register is set to "0" (interrupt disabled).
Fxxx: Interrupt factor flag
Indicate the status of interrupt factors generated.
When read
Read "1": Interrupt factor generated
Read "0": No interrupt factor generated
When written using the reset-only method (default)
Write "1": Factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Factor flag is set
Write "0": Factor flag is reset
The interrupt factor flag is set to "1" when an interrupt factor occurs in each peripheral circuit.
If the following conditions are met at this time, an interrupt is generated to the CPU:
1. The corresponding bit of the interrupt enable register is set to "1".
2. No other interrupt request of higher priority has occurred.
3. The IE bit of the PSR is set to "1" (interrupt enabled).
4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).
When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt
request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of
IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.
The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and
interrupt priority registers are set.
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and the
PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the
IE bit to "1" or executing the reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set
up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse
these two conditions.
The interrupt factor flag becomes indeterminate when initially reset, so be sure to reset the flag in the software
application.