
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-16
EPSON
S1C33T01 FUNCTION PART
P8TM2–P8TM0: 8-bit timer interrupt level (D[2:0]) / 8-bit timer, serial I/F Ch.0 interrupt priority register (0x40269)
Set the priority level of the 8-bit programmable timer interrupt in the range of 0 to 7.
At initial reset, the content of the P8TM register becomes indeterminate.
E8TU0: Timer 0 interrupt enable (D0) / 8-bit timer interrupt enable register (0x40275)
E8TU1: Timer 1 interrupt enable (D1) / 8-bit timer interrupt enable register (0x40275)
E8TU2: Timer 2 interrupt enable (D2) / 8-bit timer interrupt enable register (0x40275)
E8TU3: Timer 3 interrupt enable (D3) / 8-bit timer interrupt enable register (0x40275)
E8TU4: Timer 4 interrupt enable (D0) / 8-bit timer interrupt enable register (0x40278)
E8TU5: Timer 5 interrupt enable (D1) / 8-bit timer interrupt enable register (0x40278)
Enables or disables generation of an interrupt to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
E8TUx is the interrupt enable bit which controls the interrupt generated by each timer. The interrupt set to "1" by
this bit is enabled, and the interrupt set to "0" by this bit is disabled.
At initial reset, E8TUx is set to "0" (interrupt disabled).
F8TU0: Timer 0 interrupt factor flag (D0) / 8-bit timer interrupt factor flag register (0x40285)
F8TU1: Timer 1 interrupt factor flag (D1) / 8-bit timer interrupt factor flag register (0x40285)
F8TU2: Timer 2 interrupt factor flag (D2) / 8-bit timer interrupt factor flag register (0x40285)
F8TU3: Timer 3 interrupt factor flag (D3) / 8-bit timer interrupt factor flag register (0x40285)
F8TU4: Timer 4 interrupt factor flag (D0) / 8-bit timer interrupt factor flag register (0x40288)
F8TU5: Timer 5 interrupt factor flag (D1) / 8-bit timer interrupt factor flag register (0x40288)
Indicates the interrupt generation status of the 8-bit programmable timer.
When read
Read "1": Interrupt factor has occurred
Read "0": No interrupt factor has occurred
When written using the reset-only method (default)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows.
At this time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher priority has been generated.
3. The IE bit of the PSR is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.
When using the interrupt factor of the 8-bit programmable timer to request IDMA, note that even when the above
conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If
interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data
transfer by IDMA is completed.
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
interrupt enable and interrupt priority registers are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).