II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-16
EPSON
S1C33T01 FUNCTION PART
Table 5.3
Control Bits of Interrupt Controller (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
F16TC3
F16TU3
–
F16TC2
F16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
X
–
X
–
R/W
–
R/W
–
0 when being read.
0040283
(B)
1 Factor is
generated
0 No factor is
generated
16-bit timer 2/3
interrupt factor
flag register
–
1 Factor is
generated
0 No factor is
generated
–
F16TC5
F16TU5
–
F16TC4
F16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
X
–
X
–
R/W
–
R/W
–
0 when being read.
0040284
(B)
1 Factor is
generated
0 No factor is
generated
16-bit timer 4/5
interrupt factor
flag register
–
1 Factor is
generated
0 No factor is
generated
–
–
F8TU3
F8TU2
F8TU1
F8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
–
X
–
R/W
0 when being read.
0040285
(B)
1 Factor is
generated
0 No factor is
generated
8-bit timer
interrupt factor
flag register
–
FSTX1
FSRX1
FSERR1
FSTX0
FSRX0
FSERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
–
X
–
R/W
0 when being read.
0040286
(B)
1 Factor is
generated
0 No factor is
generated
Serial I/F Ch.0/1
interrupt factor
flag register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
–
X
–
R/W
0 when being read.
0040287
(B)
1 Factor is
generated
0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
–
E8TU1
E8TU0
D7–2
D1
D0
reserved
8-bit timer 5 underflow
8-bit timer 4 underflow
–
X
–
R/W
0 when being read.
0040288
(B)
8-bit timer
interrupt factor
flag register
–
Factor is
generated
No factor is
generated
10
–
FSTX3
FSRX3
FSERR3
FSTX2
FSRX2
FSERR2
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.3 transmit buffer empty
SIF Ch.3 receive buffer full
SIF Ch.3 receive error
SIF Ch.2 transmit buffer empty
SIF Ch.2 receive buffer full
SIF Ch.2 receive error
–
X
–
R/W
0 when being read.
0040289
(B)
1 Factor is
generated
0 No factor is
generated
Serial I/F
Ch.2/3
interrupt factor
flag register
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
0040290
(B)
1 IDMA
request
0 Interrupt
request
Port input 0–3,
high-speed
DMA, 16-bit
timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
R/W
0040291
(B)
1 IDMA
request
0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
R/W
0040292
(B)
1 IDMA
request
0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register