TM Family Datasheet Page 68 of 81 June 2009 – " />
參數(shù)資料
型號(hào)： PI7C9X20505GPBNDE
廠商： Pericom
文件頁數(shù)： 65/81頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告： Copper Wire Change 26/Sept/2011
標(biāo)準(zhǔn)包裝： 90
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，5 端口/5 線道
接口： PCI Express
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 68 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
7.2.98
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and
1C0h
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-2 Table Entry Size in 4 Bits
63 - 56
55 - 48
47 - 40
39 - 32
31 - 24
23 - 16
15 - 8
7 - 0
Byte Location
Phase
[15:14]
Phase
[13:12]
Phase
[11:10]
Phase
[9:8]
Phase
[7:6]
Phase
[5:4]
Phase
[3:2]
Phase
[1:0]
00h
Phase
[31:30]
Phase
[29:28]
Phase
[27:26]
Phase
[25:24]
Phase
[23:22]
Phase
[21:20]
Phase
[19:18]
Phase
[17:16]
08h
Phase
[47:46]
Phase
[45:44]
Phase
[43:42]
Phase
[41:40]
Phase
[39:38]
Phase
[37:36]
Phase
[35:34]
Phase
[33:32]
10h
Phase
[63:62]
Phase
[61:60]
Phase
[59:58]
Phase
[57:56]
Phase
[55:54]
Phase
[53:52]
Phase
[51:50]
Phase
[49:48]
18h
Phase
[79:78]
Phase
[77:76]
Phase
[75:74]
Phase
[73:72]
Phase
[71:70]
Phase
[69:68]
Phase
[67:66]
Phase
[65:64]
20h
Phase
[95:94]
Phase
[93:92]
Phase
[91:90]
Phase
[89:88]
Phase
[87:86]
Phase
[85:84]
Phase
[83:82]
Phase
[81:80]
28h
Phase
[111:110]
Phase
[109:108]
Phase
[107:106]
Phase
[105:104]
Phase
[103:102]
Phase
[101:100]
Phase
[99:98]
Phase
[97:96]
30h
Phase
[127:126]
Phase
[125:124]
Phase
[123:122]
Phase
[121:120]
Phase
[119:118]
Phase
[117:116]
Phase
[115:114]
Phase
[113:112]
38h
7.2.99
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Extended
Capabilities ID
RO
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
7.2.100
CAPABILITY VERSION – OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Capability Version
RO
Read as 1h. Indicates PCIe Base Specification REV. 1.0a.
Reset to 1h.
7.2.101
NEXT ITEM POINTER REGISTER – OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Next Capability
Offset
RO
Read as 000h. No other ECP registers.
Reset to 000h.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPNDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays
PI7C9X2G303ELAEVB 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA
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