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PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 27 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
ADDRESS
PCI CFG
OFFSET
DESCRIPTION
B0h(port 0~4)
B0h : Bit [13]
A8h(Port 0~4)
A8h: Bit [14:13]
Power Management Capability Disable for Port 0~4
Bit [7] : Disable Power Management Capability
RefClk ppm Difference for Port 0 ~ 4
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
10h
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 0
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
11h
84h (Port 0)
84h: Bit [31:24]
Power Management Data for Port 0
Bit [15:8]: read only as Data register
12h
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 1
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
13h
84h (Port 1)
84h: Bit [31:24]
Power Management Data for Port 1
Bit [15:8] – read only as Data register
14h
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 2
Bit [0]: No_Soft_Reset
Power Management Capability for Port 2
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
15h
84h (Port 2)
84h: Bit [31:24]
Power Management Data for Port 2
Bit [15:8] – read only as Data register
16h
84h (Port 3)
84h: Bit [3]
80h (Port 3)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 3
Bit [0]: No_Soft_Reset
Power Management Capability for Port 3
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
17h
84h (Port 3)
84h: Bit [31:24]
Power Management Data for Port 3
Bit [15:8] – read only as Data register
18h
84h (Port 4)
84h: Bit [3]
80h (Port 4)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
No_Soft_Reset for Port 4
Bit [0]: No_Soft_Reset
Power Management Capability for Port 4
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state