TM Family Datasheet Page 64 of 81 June 2009 – " />
參數(shù)資料
型號(hào)： PI7C9X20505GPBNDE
廠商： Pericom
文件頁(yè)數(shù)： 61/81頁(yè)
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告： Copper Wire Change 26/Sept/2011
標(biāo)準(zhǔn)包裝： 90
系列： GreenPacket™
應(yīng)用： 封裝開(kāi)關(guān)，5 端口/5 線道
接口： PCI Express
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 64 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
6:4
Low Priority
Extended VC Count
RO
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
7
Reserved
RO
Reset to 0b.
9:8
Reference Clock
RO
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
11:10
Port Arbitration
Table Entry Size
RO
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
31:12
Reserved
RO
Reset to 0.
7.2.88
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
VC Arbitration
Capability
RO
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Switch supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000011b.
23:8
Reserved
RO
Reset to 0.
31:24
VC Arbitration Table
Offset
RO
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 03h.
7.2.89
PORT VC CONTROL REGISTER – OFFSET 14Ch
BIT
FUNCTION
TYPE
DESCRIPTION
0
Load VC Arbitration
Table
RW
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
3:1
VC Arbitration
Select
RW
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Switch are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
15:4
Reserved
RO
Reset to 0.
7.2.90
PORT VC STATUS REGISTER – OFFSET 14Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
VC Arbitration Table
Status
RO
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
Reset to 0b.
31:17
Reserved
RO
Reset to 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPNDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays
PI7C9X2G303ELAEVB 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA
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