TM Family Datasheet Page 23 of 81 June 2009 – " />
參數(shù)資料
型號： PI7C9X20505GPBNDE
廠商： Pericom
文件頁數(shù)： 16/81頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告： Copper Wire Change 26/Sept/2011
標準包裝： 90
系列： GreenPacket™
應用： 封裝開關，5 端口/5 線道
接口： PCI Express
封裝/外殼： 256-BGA
供應商設備封裝： 256-PBGA（17x17）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 23 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
5.8
PORT ARBITRATION
Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be
forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted
Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC
channel. It means that each port has two port arbitration circuitries for VC0 and VC1 respectively. At upstream port,
in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the
arbitration loop to get the service in Virtual Channel 0.
5.9
VC ARBITRATION
After port arbitration, VC arbitration is executed among different VC channels within the same source. Three
arbitration algorithms are provided to choose the appropriate VC. They are respectively Strict Priority, Round Robin
or Weighted Round Robin.
5.10
FLOW CONTROL
PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient. The
transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has
enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free
buffer space to an opposite transmitter to avoid packet stale. In this switch, each port has separate queues for
different traffic types and the credits are on the fly sent to data link layer, which compares the current available
credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the
credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at
each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other
ingress ports for gating the packet transmission.
5.11
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION)
The transmit portion of transaction layer performs the following functions. They are to construct the all types of
forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e.
configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an
upstream port.
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相關代理商/技術參數(shù)
參數(shù)描述
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPNDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays
PI7C9X2G303ELAEVB 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA
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