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參數(shù)資料
| 型號(hào)： | PI7C9X20505GPBNDE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 32/81頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 256BGA |
| 產(chǎn)品變化通告： | Copper Wire Change 26/Sept/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開關(guān)，5 端口/5 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 38 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
31:24
Secondary Latency
Timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
7:4
I/O Base Address
[15:12]
RW
Defines the bottom address of the I/O address range for the Bridge to
determine when to forward I/O transactions from one interface to the other.
The upper 4 bits correspond to address bits [15:12] and are writable. The
lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The
upper 16 bits corresponding to address bits [31:16] are defined in the I/O base
address upper 16 bits address register.
Reset to 0h.
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
11:8
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
15:12
I/O Limit Address
[15:12]
RW
Defines the top address of the I/O address range for the Bridge to determine
when to forward I/O transactions from one interface to the other. The upper
4 bits correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16
bits corresponding to address bits [31:16] are defined in the I/O limit address
upper 16 bits address register.
Reset to 0h.
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
20:16
Reserved
RO
Reset to 00000b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the secondary side of the port in a Switch.
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
26:25
DEVSEL_L timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RO
Set to 1 (by a completer) whenever completing a request in the secondary side
using Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status in the secondary side.
Reset to 0b.
29
Received Master
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status in secondary side.
Reset to 0b.
30
Received System
RWC
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPNDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays |
| PI7C9X2G303ELAEVB | 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA |
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