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| 型號： | PI7C9X20505GPBNDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 6/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 256BGA |
| 產(chǎn)品變化通告： | Copper Wire Change 26/Sept/2011 |
| 標準包裝： | 90 |
| 系列： | GreenPacket™ |
| 應用： | 封裝開關，5 端口/5 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 14 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
NAME
PIN
TYPE
DESCRIPTION
GPIO [7:0]
L2, L1, K5,
K4, K3, K2,
J6, J5
I/O
General Purpose Input and Output: These eight general-purpose
pins are programmed as either input-only or bi-directional pins by
writing the GPIO output enable control register.
When SMBus is implemented, GPIO[7:5] act as the SMBus address
pins, which set Bit 2 to 0 of the SMBus address.
HIDRV
L6
I
High Driver Control: This mode bit is for increasing the nominal
value of the lane’s driver current level. (See Sec. 5.1 for more detailed
descriptions) By default, it is set to ‘0’ without pin strapped.
LODRV
M2
I
Low Driver Control: This mode bit is for decreasing the nominal
value of the lane’s driver current level. (See Sec. 5.1 for more detailed
descriptions) By default, it is set to ‘0’ without pin strapped.
DTX [3:0]
N1, M6, M5,
M3
I
Driver Current Level Control: This 4-bit digital word is to control
the driver current level. (See Sec. 5.1 for more detailed descriptions)
By default, they are set to “0000” without pin strapped.
DEQ [3:0]
P1, N5, N4,
N2
I
Driver Equalization Level Control: This 4-bit digital word is to
control the driver equalization level. (See Sec. 5.1 for more detailed
descriptions) By default, they are set to “1000” without pin strapped.
RXEQCTL [1:0]
P4, P3
I
Receiver Equalization Level Control: This 2-bit digital word is to
control the receiver equalization level. By default, they are set to “00”
without pin strapped.
RXTERMADJ [1:0]
T3, R2
I
Receive Termination Adjustment: A control bus to adjust the receive
termination resistor value. By default, they are set to “00” without pin
strapped.
TXTERMADJ [1:0]
T2, R1
I
Transmit Termination Adjustment: A control bus to adjust the
transmit termination resistor value. By default, they are set to “00”
without pin strapped.
TEST1
L4
I
Test1: This pin is for internal test purpose. Test1 should be tied to
ground through a pull-down resistor.
TEST2
TEST3
TEST4
TEST5
D4
D8
E8
E7
I
Test2/3/4/5: These pins are for internal test purpose. Test2, Test3,
Test4 and Test5 should be tied to 3.3V through a pull-up resistor.
TEST6
E14
I
Test6: This pin is for internal test purpose. Test6 should be connected
to an (475 ohm +/- 1%) external resistor to Vss.
NC
A3, A5, A7,
A9, B1, B3,
B5, B7, B9,
C1, D12,
D13, E1, E2,
F3, F12, F13,
H12, H13,
R3, R5,
Not Connected: These pins can be just left open.
3.5
JTAG BOUNDARY SCAN SIGNALS
NAME
PIN
TYPE
DESCRIPTION
TCK
L12
I
Test Clock: Used to clock state information and data into and out of
the chip during boundary scan. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
TMS
L13
I
Test Mode Select: Used to control the state of the Test Access Port
controller. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be pulled low through a
5.1K pull-down resistor.
TDO
M13
O
Test Data Output: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data out of the Test Access Port (TAP) in a serial bit
stream. When JTAG boundary scan function is not implemented, this
pin should be left open (NC).
TDI
L14
I
Test Data Input: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data and instructions into the TAP in a serial bit
stream. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be left open (NC).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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