TM Family Datasheet Page 5 of 81 June 2009 – R" />
參數(shù)資料
型號： PI7C9X20505GPBNDE
廠商： Pericom
文件頁數(shù)： 45/81頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告： Copper Wire Change 26/Sept/2011
標準包裝： 90
系列： GreenPacket™
應用： 封裝開關，5 端口/5 線道
接口： PCI Express
封裝/外殼： 256-BGA
供應商設備封裝： 256-PBGA（17x17）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 5 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
3.2
PORT CONFIGURATION SIGNALS .......................................................................................................12
3.3
HOT PLUG SIGNALS ...............................................................................................................................13
3.4
MISCELLANEOUS SIGNALS..................................................................................................................13
3.5
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................14
3.6
POWER PINS.............................................................................................................................................15
4
PIN ASSIGNMENTS .........................................................................................................................................16
4.1
PIN LIST OF 256-PIN PBGA......................................................................................................................16
5
FUNCTIONAL DESCRIPTION.......................................................................................................................18
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................18
5.2
DATA LINK LAYER (DLL)......................................................................................................................20
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................20
5.4
ROUTING ..................................................................................................................................................20
5.5
TC/VC MAPPING......................................................................................................................................21
5.6
QUEUE.......................................................................................................................................................21
5.6.1
PH ....................................................................................................................................................... 21
5.6.2
PD ....................................................................................................................................................... 21
5.6.3
NPHD ................................................................................................................................................. 21
5.6.4
CPLH .................................................................................................................................................. 21
5.6.5
CPLD .................................................................................................................................................. 22
5.7
TRANSACTION ORDERING...................................................................................................................22
5.8
PORT ARBITRATION ..............................................................................................................................23
5.9
VC ARBITRATION ...................................................................................................................................23
5.10
FLOW CONTROL .....................................................................................................................................23
5.11
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................23
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................24
6.1
EEPROM INTERFACE .............................................................................................................................24
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 24
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 24
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 24
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 26
6.2
SMBUS INTERFACE .................................................................................................................................32
7
REGISTER DESCRIPTION .............................................................................................................................33
7.1
REGISTER TYPES ....................................................................................................................................33
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS....................................................................33
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 35
7.2.2
DEVICE ID REGISTER – OFFSET 00h............................................................................................. 35
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 35
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 36
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 36
7.2.6
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 36
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相關代理商/技術參數(shù)
參數(shù)描述
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPNDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays
PI7C9X2G303ELAEVB 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA
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