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FEDL60852A-03
1Semiconductor
ML60852A
15/81
(5) Data packet transmission and reception procedure during bulk transfer and interrupt transfer modes
The ML60852A is normally used on the peripheral device side. In this method of use, the ML60852A is connected
on one side to the host via the USB bus and is connected on the other side via a parallel interface to the local
microcontroller (local MCU) inside the peripheral device.
Transfer of data is the major function in all types of transfer modes other than the control transfer mode. When
carrying out transfer of data packets between the ML60852A and the host, the following packet communication is
carried out via the USB bus for data transfer of each packet.
(a) Token packet transfer (IN token or OUT token) from the host to the ML60852A.
(b) Data packet transfer in the desired direction (from the host to the device or from the device to the host).
(c) Transfer of handshake packet in a direction opposite to that of the data packet.
When packet transfer is completed normally, an ACK packet is returned in step (c) and the operation proceeds
to the next packet transfer.
The ML60852A requests the local MCU to transmit or receive a packet of data by asserting the
INTR pin. The
interrupt cause will be “packet ready”. The transmit packet ready interrupt is one that requests that the packet
of data to be transmitted be written in the transmit FIFO, and the receive packet ready interrupt is one that
requests the local MCU to read out the data that has been received and stored in the receive FIFO.
The above procedures of transferring one packet of data are explained below for transmission and reception
separately.
1)
During transmission
The local MCU writes one packet of data that has to be transmitted in the transmit FIFO of the corresponding
EP in the ML60852A, and sets the transmit packet ready bit of the corresponding EP status register of the
ML60852A. When the host transmits an IN token packet to the ML60852A, the ML60852A transmits to the
host the data packet stored in the above transmit FIFO. When the host receives one data packet normally, it
returns an ACK packet to the ML60852A. Consequently, the ML60852A resets the transmit packet ready
status, thereby completing the transfer of one data packet over the USB bus. When the transmit packet ready
status is reset, the ML60852A gives a request to the local MCU in terms of a transmit packet ready interrupt
thereby prompting the local MCU to write the next packet of data to be transmitted.
2)
During reception
The host sends to the ML60852A an OUT token followed by a data packet. The ML60852A stores the
received data packet in the receive FIFO of the corresponding EP. When it is confirmed that all the data
packets have been accumulated and that there is no error, the ML60852A returns an ACK packet to the host.
At the same time, the receive packet ready bit of the corresponding EP status register will also be set and a
request is sent to the local MCU in terms of an interrupt. Upon receiving this interrupt, the local MCU reads
out the received data from the ML60852A and resets the receive packet ready bit.