- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98023 > ML60852A (LAPIS SEMICONDUCTOR CO LTD) UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 13/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
FEDL60852A-03
1Semiconductor
ML60852A
19/81
(2) EP0 Receive packet ready interrupt
This is used mainly during the reception of a data packet in a control write transfer.
Operation
Source of operation
Description (conditions, responses, etc.)
EP0 Receive packet ready
interrupt generation
ML60852A
The EP0 receive packet ready bit (D0 of EP0STAT) is
asserted during a control write transfer when the
processing has changed from the setup stage to the data
stage, and the ML60852A has detected EOP of the data
packet and has stored the data without error in the EP0
receive FIFO. The end of a packet is recognized when an
EOP has arrived in the cases of both full packets and short
packets.
An interrupt is generated at this time, if the EP0 receive
packet ready interrupt enable bit (D6 of INTENBL1) has
been asserted.
(EOP: End of packet)
End of EP0 receive
packet ready interrupt
Local MCU (firmware)
In the case of EP0 reception, after the number of bytes of
the EP0 receive FIFO data indicated by the EP0 receive
byte count register (EP0RXCNT) has been read, write a “1”
to the EP0 receive packet ready bit (bit D0 of EP0STAT).
(This status is reset when a “1” is written in this bit.)
Note:
A short packet is a packet with a number of bytes less than the maximum packet size.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML63187-XXXGA | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP128 |
| ML63193-XXXWA | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC128 |
| ML64168-XXX | 4-BIT, MROM, 0.7 MHz, MICROCONTROLLER, UUC80 |
| ML64P168-NGP | 4-BIT, OTPROM, 0.7 MHz, MICROCONTROLLER, PQFP80 |
| ML64P168-NGA | 4-BIT, OTPROM, 0.7 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。