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參數(shù)資料
| 型號(hào)： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 65/82頁 |
| 文件大小： | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
67/81
Relationship between the transmit FIFO status, register status of each EP and INTR signal
Note: The following table assumes that the transmit packet ready status bit (D1 of EPnSTAT) is set (to ‘1’)
immediately after writing transmit data to each layer of the EPnFIFO.
Trnsmit FIFO status
Register status of each EP
Packet ready interrupt enable bit = 1
Transmit packet ready control bit = 0
Register status of each EP
Packet ready interrupt enable bit = 1
Transmit packet ready control bit = 1
Both layers are not empty
INTR signal is de-asserted
One layer is empty and
Other layer is not empty
INTR signal is asserted
INTR signal is de-saaerted
Both layers are empty
INTR signal is asserted
* Definition of transmit FIFO “empty”
When one of the following two conditions is satisfied, transmit FIFO is empty.
(1) In the early transmit stage just after the corresponding endpoint configuration, the local MCU has not written a
“1” into the D1 bit of the EPnSTAT register yet.
(2) The transmit data written by the local MCU is transferred to HOST and an ACK signal is returned from HOST.
* When the packet ready interrupt enable bit of the corresponding EP is de-asserted, the INTR signal is de-asserted
irrespective of the status of transmit FIFO.
(When other interrupt factor is generated, the INTR signal is asserted.)
The interrupt factor of the transmit packet ready interrupt can be changed by using the transmit packet ready
control bit.
For instance, if one layer of transmit FIFO is empty and other layer is not empty,
The asserted INTR signal is de-asserted by changing the transmit packet ready control bit to “1” from “0”.
The de-asserted INTR signal is asserted by changing the transmit packet ready control bit to “0” from “1”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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